ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 135

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: These registers have an alternate definition for E1 mode. See E1RAF, E1RNAF, and E1RSiAF.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: This register has an alternate definition for T1 mode. See T1RSLC1.
Bit 7: International Bit (Si).
Bit 6: Frame Alignment Signal Bit (0).
Bit 5: Frame Alignment Signal Bit (0).
Bit 4: Frame Alignment Signal Bit (1).
Bit 3: Frame Alignment Signal Bit (1).
Bit 2: Frame Alignment Signal Bit (0).
Bit 1: Frame Alignment Signal Bit (1).
Bit 0: Frame Alignment Signal Bit (1).
(MSB) 7
S=1
M2
C8
Si
0
7
0
T1RSLC1, T1RSLC2, T1RSLC3 (T1 Mode)
Receive SLC-96 Data Link Registers 1 to 3
064h, 065h, 066h + (200h x n): where n = 0 to 3, for Ports 1 to 4
E1RAF (E1 Mode)
E1 Receive Align Frame Register
064h + (200h x n): where n = 0 to 3, for Ports 1 to 4
M1
C7
S4
6
0
6
0
0
S=0
C6
S3
5
0
5
0
0
S=1
C5
S2
4
0
135 of 273
4
1
0
S=0
C4
S1
3
0
3
1
0
C11
C3
A2
2
0
C10
2
0
0
C2
A1
1
0
0 (LSB)
M3
C1
C9
0
1
1
0
T1RSLC1
T1RSLC2
T1RSLC3
0
1
0