ds26524 Maxim Integrated Products, Inc., ds26524 Datasheet - Page 166

• Manufacturer Part Number: ds26524
• Description: Ds26524 Quad T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: For E1 mode, see RIM3.
Bit 7: Loss of Receive Clock Condition Clear (LORCC).
Bit 6: Spare Code Detected Condition Clear (LSPC).
Bit 5: Loop-Down Code Detected Condition Clear (LDNC).
Bit 4: Loop-Up Code Detected Condition Clear (LUPC).
Bit 3: Loss of Receive Clock Condition Detect (LORCD).
Bit 2: Spare Code Detected Condition Detect (LSPD).
Bit 1: Loop-Down Code Detected Condition Detect (LDND).
Bit 0: Loop-Up Code Detected Condition Detect (LUPD).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
LORCC
7
0
RIM3 (T1 Mode)
Receive Interrupt Mask Register 3
0A2h + (200h x n): where n = 0 to 3, for Ports 1 to 4
LSPC
6
0
LDNC
5
0
166 of 273
LUPC
0
4
LORCD
3
0
LSPD
2
0
LDND
1
0
LUPD
0
0