mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 124

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mc68hc08qa24

Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Clock Generator Module (CGM)
9.6.3 PLL Programming Register
Technical Data
122
Address:
The PLL programming register (PPG) contains the programming
information for the modulo feedback divider and the programming
information for the hardware configuration of the VCO.
MUL7–MUL4 — Multiplier Select Bits
Reset:
Read:
Write:
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See
Circuit
modulo feedback divider the same as a value of $1. Reset initializes
these bits to $6 to give a default multiply value of 6.
$001E
MUL7
Bit 7
Table 9-1. VCO Frequency Multiplier (N) Selection
0
(PLL).) A value of $0 in the multiplier select bits configures the
Clock Generator Module (CGM)
Figure 9-7. PLL Programming Register (PPG)
MUL7–MUL4
MUL6
0000
0001
0010
0011
1101
1110
1111
6
1
MUL5
5
1
MUL4
4
0
VCO Frequency Multiplier (N)
VRS7
9.4.2 Phase-Locked Loop
3
0
13
14
15
VRS6
1
1
2
3
Freescale Semiconductor
2
1
MC68HC08QA24
VRS5
1
1
VRS4
Bit 0
0

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