mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 179

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mc68hc08qa24

Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
14.4.7 COPS (COP Short Timeout)
14.5 COP Control Register
14.6 Interrupts
14.7 Monitor Mode
MC68HC08QA24
Freescale Semiconductor
Address: $FFFF
The COPS bit selects the state of the COP short timeout bit (COPS) in
the MOR ($001F). Timeout periods can be (2
CGMXCLK cycles. (See
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
Electrical
Reset:
Read:
Write:
Computer Operating Properly (COP)
Bit 7
Figure 14-2. COP Control Register (COPCTL)
Characteristics) is present on the IRQ pin or on the RST pin.
6
5.4 Mask Option
5
Low byte of reset vector
Unaffected by reset
Clear COP counter
4
Computer Operating Properly (COP)
3
Register.)
18
DD
–2
+ V
4
2
) or (2
HI
(see
13
1
Technical Data
–2
23.5 DC
4
)
Bit 0
177

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