mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 266

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI)
18.13.3 SPSCK (Serial Clock)
18.13.4 SS (Slave Select)
Technical Data
264
NOTE:
The serial clock synchronizes data transmission between master and
slave devices. In a master MCU, the SPSCK pin is the clock output. In a
slave MCU, the SPSCK pin is the clock input. In full duplex operation, the
master and slave MCUs exchange a byte of data in eight serial clock
cycles.
When enabled, the SPI controls data direction of the SPSCK pin
regardless of the state of the data direction register of the shared I/O
port.
The SS pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS is used to select a slave.
For CPHA = 0, the SS is used to define the start of a transmission. (See
18.6 Transmission
transmission, the SS must be toggled high and low between each byte
transmitted for the CPHA = 0 format. However, it can remain low
throughout the transmission for the CPHA = 1 format. See
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See
SPI Status and Control
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a
high-impedance state. The slave SPI ignores all incoming SPSCK
clocks, even if a transmission already has begun.
MASTER SS
MISO/MOSI
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
Serial Peripheral Interface (SPI)
Figure 18-12. CPHA/SS Timing
BYTE 1
Formats.) Since it is used to indicate the start of a
Register.)
BYTE 2
Freescale Semiconductor
BYTE 3
MC68HC08QA24
Figure
18.14.2
18-12.