mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 267
mc68hc08qa24
Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC08QA24.pdf
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18.13.5 V
MC68HC08QA24
Freescale Semiconductor
SS
(Clock Ground)
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See
SS pin to set the MODF flag, the MODFEN bit in the SPSCK register
must be set. If the MODFEN bit is low for an SPI master, the SS pin can
be used as a general-purpose I/O under the control of the data direction
register of the shared I/O port. With MODFEN high, it is an input-only pin
to the SPI regardless of the state of the data direction register of the
shared I/O port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the data register.
(See
V
for the port output buffers. To reduce the ground return path loop and
minimize radio frequency (RF) emissions, connect the ground pin of the
slave to the V
X = don’t care
SPE SPMSTR MODFEN
SS
0
1
1
1
is the ground return for the serial clock pin, SPSCK, and the ground
Table
X
0
1
1
Serial Peripheral Interface (SPI)
18-4.)
SS
pin.
X
X
0
1
Table 18-4. SPI Configuration
Master without MODF
18.7.2 Mode Fault
SPI Configuration
Master with MODF
Not enabled
Slave
Error.) For the state of the
Serial Peripheral Interface (SPI)
General-purpose I/O;
General-purpose I/O;
State of SS Logic
SS ignored by SPI
SS ignored by SPI
Input-only to SPI
Input-only to SPI
Technical Data
265
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