mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 135

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

10.3 SIM Bus Clock Control and Generation
10.3.1 Bus Timing
10.3.2 Clock Startup from POR or LVI Reset
MC68HC08QA24
Freescale Semiconductor
OSC1
PLL
CGMVCLK
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
come from either an external oscillator or from the on-chip PLL. (See
Section 9. Clock Generator Module
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. (See
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after 4096 CGMXCLK cycles.
The RST pin is driven low by the SIM during this entire period. The bus
clocks start upon completion of the timeout.
MONITOR MODE
SELECT
CIRCUIT
CLOCK
USER MODE
BCS
CGM
Figure 10-3. CGM Clock Signals
PTC3
System Integration Module (SIM)
÷
2
Section 9. Clock Generator Module
A
B S*
*When S = 1,
CGMOUT = B
CGMXCLK
CGMOUT
(CGM).)
Figure
System Integration Module (SIM)
÷
10-3. This clock can
SIM COUNTER
2
SIM
GENERATORS
BUS CLOCK
Technical Data
(CGM).)
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