mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 300
mc68hc08qa24
Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC08QA24.pdf
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Timer Interface A (TIMA)
20.8 I/O Signals
20.8.1 TIMA Clock Pin (PTF3/TACLK)
Technical Data
298
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
Port F shares one of its pins with the TIMA. Port E shares two of its pins
with the TIMA. PTF3/TACLK is an external clock input to the TIMA
prescaler. The two TIMA channel I/O pins are PTE2/TACH0 and
PTE3/TACH1.
PTF3/TACLK is an external clock input that can be the clock source for
the TIMA counter instead of the prescaled internal bus clock. Select the
PTF3/TACLK input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See
minimum TCLK pulse width, TCLK
See
number 6.
The maximum TCLK frequency is the least: 4 MHz or bus frequency ÷ 2.
PTF3/TACLK is available as a general-purpose I/O pin or ADC channel
when not used as the TIMA clock input. When the PTF3/TACLK pin is
the TIMA clock input, it is an input regardless of the state of the DDRF3
bit in data direction register F.
23.8 5.0 Vdc ± 10% Serial Peripheral Interface (SPI) Timing
Timer Interface A (TIMA)
20.9.1 TIMA Status and Control
------------------------------------ -
bus frequency
1
LMIN
or TCLK
+
t
SU
HMIN
Register.) The
Freescale Semiconductor
, is:
MC68HC08QA24
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