mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 370

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mc68hc08qa24

Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
CAN Controller
22.14.3 MSCAN08 Bus Timing Register 0
Technical Data
368
NOTE:
Address:
SJW1 and SJW0 — Synchronization Jump Width Bits
BRP5–BRP0 — Baud Rate Prescaler Bits
The CBTR0 register can be written only if the SFTRES bit in the
MSCAN08 module control register is set.
Reset:
Read:
Write:
The synchronization jump width (SJW) defines the maximum number
of system clock (t
lengthened, to achieve resynchronization on data transitions on the
bus (see
These bits determine the MSCAN08 system clock cycle time (t
which is used to build up the individual bit timing, according to
Table
BRP5
0
0
0
0
1
:
:
SJW1
Figure 22-16. CAN Bus Timing Register 0 (CBTR0)
$0502
SJW1
Bit 7
0
0
1
1
22-5.
0
BRP4
Table
0
0
0
0
1
:
:
Table 22-4. Synchronization Jump Width
SJW0
CAN Controller
6
0
22-4).
Table 22-5. Baud Rate Prescaler
BRP3
SCL
0
0
0
0
1
SJW0
:
:
) cycles by which a bit may be shortened, or
0
1
0
1
BRP5
5
0
BRP2
0
0
0
0
1
:
:
BRP4
4
0
BRP1
Synchronization Jump Width
0
0
1
1
1
:
:
BRP3
3
0
BRP0
2 t
3 t
4 t
1 t
0
1
0
1
1
:
:
SCL
SCL
SCL
SCL
BRP2
Freescale Semiconductor
2
0
cycles
cycles
cycles
cycle
Prescaler Value (P)
MC68HC08QA24
BRP1
1
0
64
1
2
3
4
:
:
BRP0
SCL
Bit 0
0
),

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