mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 142
mc68hc08qa24
Manufacturer Part Number
mc68hc08qa24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC08QA24.pdf
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System Integration Module (SIM)
10.6 Program Exception Control
10.6.1 Interrupts
Technical Data
140
INTERRUPT
MODULE
I BIT
R/W
IAB
IDB
DUMMY
DUMMY
Normal, sequential program execution can be changed in three different
ways:
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the return-from-interrupt
(RTI) instruction recovers the CPU register contents from the stack so
that normal processing can resume.
timing.
Figure 10-10
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced or the I bit is cleared.
(See
SP
1. Interrupts:
2. Reset
3. Break interrupts
PC – 1[7:0]
Figure 10-8. Hardware Interrupt Entry
Figure
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
SP – 1
PC – 1[15:8]
System Integration Module (SIM)
10-9.)
shows interrupt recovery timing.
SP – 2
X
SP – 3
A
SP – 4
CCR
VECT H
Figure 10-8
V DATA H
VECT L
V DATA L
shows interrupt entry
Freescale Semiconductor
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MC68HC08QA24
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