mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 298

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface A (TIMA)
20.5 Interrupts
Technical Data
296
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMA channel 0 registers (TACH0H–TACH0L)
initially control the buffered PWM output. TIMA channel 0 status control
register 0 (TASC0) controls and monitors the PWM signal from the
linked channels. MS0B takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMA overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0 percent duty
cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100 percent duty cycle output. (See
TIMA Channel Status and Control
These TIMA sources can generate interrupt requests:
•
•
TIMA overflow flag (TOF) — The TOF bit is set when the TIMA
counter value rolls over to $0000 after matching the value in the
TIMA counter modulo registers. The TIMA overflow interrupt
enable bit, TOIE, enables TIMA overflow CPU interrupt requests.
TOF and TOIE are in the TIMA status and control register.
TIMA channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIMA CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE.
Timer Interface A (TIMA)
Registers.)
Freescale Semiconductor
MC68HC08QA24
20.9.4