mc68hc08qa24 Freescale Semiconductor, Inc, mc68hc08qa24 Datasheet - Page 148

• Manufacturer Part Number: mc68hc08qa24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
10.7.2 Stop Mode
Technical Data
146
NOTE:
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the short stop recovery (SSREC) bit in
the CONFIG register ($001F). If SSREC is set, stop recovery is reduced
from the normal delay of 4096 CGMXCLK cycles down to 32. This is
ideal for applications using canned oscillators that do not require long
startup times from stop mode.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
CPUSTOP
Note: Previous data can be operand data or the STOP opcode, depending on the last instruction.
R/W
IDB
IAB
System Integration Module (SIM)
STOP ADDR
Figure 10-15. Stop Mode Entry Timing
Figure 10-15
PREVIOUS DATA
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
SAME
Freescale Semiconductor
SAME
MC68HC08QA24
SAME
SAME