at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1033
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at91sam9263
Manufacturer Part Number
at91sam9263
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet
1.AT91SAM9263.pdf
(1065 pages)
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49.2.12.3
49.2.13
49.2.13.1
49.2.13.2
49.2.13.3
49.2.13.4
6249D–ATARM–20-Dec-07
Serial Peripheral Interface (SPI)
JEDEC Standard Compatibility
PDC Data Loss
Pulse Generation on SPCK
Bad PDC Behavior when CSAAT=1 and SCBR = 1
LASTXFER (Last Transfer) Behavior
In the current configuration, SDCKE rises at the same time as SDCK while exiting self-refresh
mode. To be fully compliant with the JEDEC standard, SDCK must be STABLE before the rising
edge of SDCKE.
It is not the case in this product.
Problem Fix/Workaround
Use a fully JEDEC compliant SDRAM module.
One byte data can be lost when PDC transmits. This occurs when write accesses are performed
on the base address of any peripheral,during the PDC transfer.
Problem Fix/Workaround:
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
Problem Fix/Workaround
None.
If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are per-
formed consecutively on the same slave with an IDLE state between them, the second data is
sent twice.
Problem Fix/Workaround
None. Do not use the combination CSAAT=1 and SCBR =1.
In FIXED Mode with CSAAT bit set and in PDC Mode, the Chip Select can rise depending on the
data written in the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a
"1" in bit 24 (LASTXFER bit) of the SPI_TDR, the Chip Select rises as soon as the TXEMPTY
flag is set.
Problem Fix/Workaround
Use the CS in PIO mode when PDC Mode is required and CS has to be maintained between
transfers.
– Add a timeout for the PDC transfer and check the value of the PDC transmit counter
– Check the data integrity by a checksum.
– Avoid write access on the base address of peripherals during a PDC transfer.
– The Baudrate is odd and different from 1.
– The Polarity is set to 1.
– The Phase is set to 0 .
when the timeout elapsed.
AT91SAM9263 Preliminary
1033
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