at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 30
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at91sam9263
Manufacturer Part Number
at91sam9263
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet
1.AT91SAM9263.pdf
(1065 pages)
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9.8
9.9
9.10
9.11
9.12
30
Real-time Timer
General-purpose Backup Registers
Backup Power Switch
Advanced Interrupt Controller
Debug Unit
AT91SAM9263 Preliminary
• Windowed, prevents the processor deadlocking on the watchdog access
• Two Real-time Timers, allowing backup of time with different accuracies
• Twenty 32-bit general-purpose backup registers
• Automatic switch of VDDBU to VDDCORE guaranteeing very low power consumption on
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
• Four External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
• Vectoring
• Protect Mode
• Fast Forcing
• Composed of two functions
VDDBU while VDDCORE is present
– 32-bit Free-running back-up counter
– Integrates a 16-bit programmable prescaler running on the embedded 32.768Hz
– Alarm Register capable of generating a wake-up of the system through the
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
– Easy debugging by preventing automatic operations when protect models are
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
– Two-pin UART
oscillator
Shutdown Controller
enabled
processor
6249D–ATARM–20-Dec-07
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