at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 306

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

24.4.3
Name: DMAC_LLPx
Access: Read/Write
Reset: 0x0
The address offset for each channel is: 0x10+[x * 0x58]
For example, LLP0: 0x010, LLP1: 0x068, etc.
• LOC: Address of the next LLI
Starting address in memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not
stored because the address is assumed to be aligned to a 32-bit boundary.
The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if
block chaining is enabled.
The LLP register has two functions:
If LLP.LOC is set to 0x0, then transfers using linked lists are NOT enabled. This register must be programmed prior to
enabling the channel in order to set up the transfer type.
It (LLP.LOC != 0) contains the pointer to the next Linked Listed Item for block chaining using linked lists.
6249D–ATARM–20-Dec-07
31
23
15
7
Linked List Pointer Register for Channel x
30
22
14
6
1. The logical result of the equation LLP.LOC != 0 is used to set up the type of DMA trans-
2. The DMAC_LLPx register is also used to point to the address where write back of the
fer (single or multi-block).
control and source/destination status information occurs after block completion.
29
21
13
5
LOC
28
20
12
4
LOC
LOC
LOC
27
19
11
3
AT91SAM9263 Preliminary
26
18
10
2
25
17
9
1
0
24
16
8
0
0
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