at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1047

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.3.15
49.3.15.1
49.3.16
49.3.16.1
49.3.16.2
6249D–ATARM–20-Dec-07
UDP
UHP
Bad Data in the First IN Data Stage
Non-ISO IN Transfers
ISO OUT Transfers
Problem Fix/Workaround
Insert a delay of one TWI clock period before step 4.
All or part of the data of the first IN data Stage are not transmitted. It may then be a Zero Length
Packet. The CRC is correct. Thus the HOST may only see that the size of the received data
does not match the requested length. But even if performed again, the control transfer probably
fails.
Problem Fix/Workaround
Control transfers are mainly used at device configuration. After clearing RXSETUP, the software
needs to compute the setup transaction request before writing data into the FIFO if needed. This
time is generally greater than the minimum safe delay required above. If not, a software wait
loop after RXSETUP clear may be added at minimum cost.
Conditions:
Consider the following scenario:
Consequence: When this error occurs, the Host controller tries the same IN token again.
Problem Fix/Workaround
This problem can be avoided if the system guarantees that the status update can be completed
within the same frame.
Conditions:
Consider the following scenario:
1. The Host controller issues an IN token.
2. The Device provides the IN data in a short packet.
3. The Host controller writes the received data to the system memory.
4. The Host controller is now supposed to do two Write transactions (TD status write and
5. Host controller raises the request for the first write transaction. By the time the transac-
6. After completing the first write transaction, the Host controller skips the second write
1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the
2. When the Host controller is sending the ISO OUT data, because of system latencies,
3. While there is an underrun condition, if the Host controller is in the process of bit-stuff-
TD retirement write) to the system memory in order to complete the status update.
tion is completed, a frame boundary is crossed.
transaction.
system memory.
remaining bytes of the packet are not available. This results in a buffer underrun
condition.
ing, it causes the Host controller to hang.
AT91SAM9263 Preliminary
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