at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1044

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.3.10
49.3.10.1
49.3.10.2
49.3.11
49.3.11.1
49.3.11.2
1044
AT91SAM9263 Preliminary
SDRAM Controller
Serial Peripheral Interface (SPI)
SDCLK Clock Active after Reset
Mobile SDRAM Device Initialization Constraint
Pulse Generation on SPCK
Bad PDC Behavior when CSAAT=1 and SCBR = 1
During the power-up sequence, if VDDIOP power supply is not established whereas the
VDDCORE Power On Reset output is released, the NTRST signal is not correctly asserted. This
leads to a bad reset of the Embedded Trace Macrocell (ETM9). The ARM processor then enters
debug state and the device does not boot correctly.
Problem Fix/Workaround
After a reset, the SDRAM clock is always active leading to overconsumption in the pad.
Problem Fix/Workaround
The following sequence stops the SDRAM clock:
Using Mobile SDRAM devices that need to have their DQMx level HIGH during Mobile SDRAM
device initialization may lead to data bus contention and thus external memories on the same
EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “Don’t care” during this
phase.
Problem Fix/Workaround
Mobile SDRAM initialization must be performed in internal SRAM.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
Problem Fix/Workaround
None.
If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are per-
formed consecutively on the same slave with an IDLE state between them, the second data is
sent twice.
Problem Fix/Workaround
1. Connect NTRST pin to NRST pin to ensure that a correct powering sequence takes
2. Connect NTRST to GND if no debug capabilities are required.
1. Set the bit LPCB in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to
place in all cases.
complete.
– The Baudrate is odd and different from 1.
– The Polarity is set to 1.
– The Phase is set to 0 .
6249D–ATARM–20-Dec-07