at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1034

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.2.13.5
49.2.13.6
49.2.13.7
49.2.13.8
1034
AT91SAM9263 Preliminary
Baudrate set to 1
Software Reset
Chip Select and Fixed Mode
SPI: Bad Serial Clock Generation on 2nd Chip Select
When Baudrate is set to 1 (i.e. when serial clock frequency equals the system clock frequency),
and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case
9,11,13 or 15), an additional pulse is generated on output SPCK. No such pulse occurs if BITS
field equals 8,10,12,14 or 16 and Baudrate = 1.
Problem Fix/Workaround
None.
If the Software reset command is performed during the same clock cycle as an event for
TXRDY, there is no reset.
Problem Fix/Workaround
Perform another a software reset.
In fixed Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip
Select 0, the output spi_size sampled by the PDC depends on the field BITS of SPI_CSR0 reg-
ister, whatever the selected Chip select may be. For example, if CSR0 is configured for a 10-bit
transfer, whereas the CSR1 is configured for an 8-bit transfer, when a transfer is performed in
Fixed mode through the PDC on Chip Select 1, the transfer is considered to be a half-word
transfer.
Problem Fix/Workaround
If a PDC transfer has to be performed in 8 bits on a Chip select y (y different from 0), the field
BITS of the CSR0 must be configured in 8 bits in the same way as the field BITS of the CSRy
Register.
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• Transmitting with the slowest chip select and then with the fastest one, then an additional
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR are not equal to 1
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
6249D–ATARM–20-Dec-07