at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 244

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

22.5.3
Figure 22-4. Read Burst with Boundary Row Access
244
SDRAMC_A[12:0]
D[31:0]
SDWE
SDCS
SDCK
RAS
CAS
AT91SAM9263 Preliminary
Border Management
col a
Row n
col b
Dna
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAM controller generates a precharge command, activates the new row and ini-
tiates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inserted between the precharge/active (t
mand. This is described in
col c
Dnb
col d
Dnc
Dnd
T
Figure 22-4
RP
= 3
Row m
below.
T
RCD
= 3
RP
col a
) command and the active/read (t
CAS = 2
col b
Dma
col c
Dmb
col d
Dmc
6249D–ATARM–20-Dec-07
col e
Dmd
RCD
Dme
) com-