at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 2
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at91sam9260-cj
Manufacturer Part Number
at91sam9260-cj
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet
1.AT91SAM9260-CJ.pdf
(790 pages)
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2
Debug Unit (DBGU)
Periodic Interval Timer (PIT)
Watchdog Timer (WDT)
Real-time Timer (RTT)
One 4-channel 10-bit Analog-to-Digital Converter
Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC)
Peripheral DMA Controller Channels (PDC)
One Two-slot MultiMedia Card Interface (MCI)
One Synchronous Serial Controller (SSC)
Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
Two 2-wire UARTs
Two Master/Slave Serial Peripheral Interfaces (SPI)
Two Three-channel 16-bit Timer/Counters (TC)
One Two-wire Interface (TWI)
IEEE
Required Power Supplies:
Available in a 208-lead PQFP Green and a 217-ball LFBGA Green Package
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
– 20-bit Interval Timer plus 12-bit Interval Counter
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
– High-current Drive I/O Lines, Up to 16 mA Each
– SDCard/SDIO and MultiMediaCard
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
– Individual Baud Rate Generator, IrDA
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Signal Control on USART0
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
– Master, Multi-master and Slave Mode Operation
– General Call Supported in Slave Mode
– 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
®
1149.1 JTAG Boundary Scan on All Digital Pins
AT91SAM9260
™
Compliant
®
Infrared Modulation/Demodulation, Manchester Encoding/Decoding
6221G–ATARM–31-Jan-08
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