at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 776

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Table 44-1.
776
Revision
6221E
6221D
AT91SAM9260
Current version appears first
Comments
PMC: In
information on Idle Mode and added Note.
SPI: Corrected information in
OVRES (SPI_SR) and data read in SPI_RDR.
TWI: New chapter inserted.
USART: In
use of internal pull up on TXD pertaining to hardware handshaking feature/Modem
mode.
In
paragraph, software reset effects (RSTRX and RSTTX in US_CR register) updated
by replacing 2nd sentence.
EMAC: Corrected status for IDLE bit in
on page
Added information on clocks in first paragraph of
Description” on page
Corrected offset values for Channel Data Register3 and Reserved space in
Section 40.6 ”Analog-to-digital Converter (ADC) User Interface” on page
Table 40-2, “ADC Register
Added
In
corrected parameter conditions to VDDBU.
In
conditions.
Errata: Added
786
Added
page
Updated
786.
Added
Updated information on programmable pull-up resistor in
Controllers” on page
Updated
In
clocking and corrected Peripheral Name for PID12, PID13 and PID14.
Placed comment on RDY/BUSY with PC13 in
Controller C,” on page
Boot Program: Added
Corrected code in
vectors example in
Updated DataFlash support for Boot ROM in
page 84
Section 32.6.2 ”Receiver and Transmitter Control” on page
Table 41-9, “32 kHz Oscillator Characteristics,” on page
Section 41.7 ”EBI Timings” on page
Table 10-1, “AT91SAM9260 Peripheral Identifiers,” on page
and
786.
to“SDRAM Controller”
Table 41-6, “Master Clock Waveform Parameters,” on page
Section 44.2.2.1 ”NAND Flash Boot does not work correctly” on page
Section 26.3 “Processor Clock Controller” on page
624.
Section 44.2.6.2 ”Bad sampling of OSCSEL” on page
Section 44.2.7.2 ”Mobile SDRAM device initialization constraint” on page
Section 6.7 “Slow Clock Selection” on page
Section 32.5.1 ”I/O Lines” on page
”Oscillators”
Section 13.4 ”DataFlash Boot” on page
Section 13.4.2 ”Structure of ARM Vector 6” on page
16.
604.
Figure 13-2, ”Clocks and DBGU Configurations” on page
36.
,
Mapping”.
Section 44.2.6.1 ”On-chip RC startup time” on page
,
Section 30.6.4 “SPI Slave Mode” on page 369
Section 44.2.7.3 ”JEDEC standard compatibility” on
759, removed sentence on EBI timings
Section 36.5.3 ”Network Status Register”
Table 13-5, “DataFlash Device,” on
Table 10-4, “Multiplexing on PIO
448, added sentence on required
Section 36.3 ”Functional
16.
Section 6.4 “PIO
83. Corrected valid
754, for Startup Time
257, updated
454, in the fourth
786.
32, added Note on
752.
84.
738,
on
784.
81.
Change Request Ref.
4322
3943
4825
4367
3326
3328
4379
4303
4267
4254
4235
4329
4219
4563
4564
3972
3504 and 3543
3406
3455
3453
4184
6221G–ATARM–31-Jan-08