at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 213

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 22-3. Read Burst, 32-bit SDRAM Access
22.5.3
6221G–ATARM–31-Jan-08
SDRAMC_A[12:0]
Border Management
D[31:0]
SDWE
SDCS
(Input)
SDCK
RAS
CAS
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAM controller generates a precharge command, activates the new row and ini-
tiates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inserted between the precharge/active (t
mand. This is described in
Row n
t
RCD
= 3
col a
Figure 22-4
CAS = 2
col b
Dna
below.
col c
Dnb
col d
RP
) command and the active/read (t
Dnc
col e
Dnd
col f
Dne
AT91SAM9260
Dnf
RCD
) com-
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