at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 760

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

44.2.5.2
44.2.6
44.2.6.1
44.2.6.2
44.2.6.3
44.2.7
44.2.7.1
760
AT91SAM9260
SDRAM Controller
Serial Peripheral Interface (SPI)
Bad sampling of OSCSEL
SDCLK Clock active after reset
Mobile SDRAM device initialization constraint
JEDEC standard compatibility
Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0
When VDDBU only is powered, either internal RC oscillator or external 32K osc may start
regardless of the setting of the OSCSEL pin. The OSCSEL pin sampling is correct after applying
VDDCORE power supply and remains correct if VDDCORE is removed.
The first power-up sequence requires both VDDBU and VDDCORE to correctly sample the
OSCSEL signal.
After a reset, the SDRAM clock is always active leading to over consumption in the pad.
The following sequence stops the SDRAM clock.
Using Mobile SDRAM devices that need to have their DQMx level HIGH during Mobile SDRAM
device initialization may lead to data bus contention and thus external memories on the same
EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “Don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
In the current revision, SDCKE rises at the same time as SDCK while exiting self-refresh mode.
To be fully compliant with the JEDEC standard, SDCK must be STABLE before the rising edge
of SDCKE.
None.
If the SPI is used in the following configuration:
then an additional pulse will be generated on output PSCK during the second transfer.
1. Set the bit LPCB in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to
• master mode
• CPOL = 1 and NCPHA = 0
• multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• transmit with the slowest chip select and then with the fastest one
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR not equal to 1
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
complete.
6221G–ATARM–31-Jan-08