at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 679

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

39.3.1
Figure 39-3. HSYNC and VSYNC Synchronization
Figure 39-4. SAV and EAV Sequence Synchronization
6221G–ATARM–31-Jan-08
Data Timing
DATA[7..0]
ISII_PCK
ISI_HSYNC
ISI_VSYNC
DATA[7..0]
ISI_PCK
The two data timings using horizontal and vertical synchronization and EAV/SAV sequence syn-
chronization are shown in
In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the
pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay pro-
grammed in the control register.
The ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface.
There are two timing reference signals, one at the beginning of each video data block SAV
(0xFF000080) and one at the end of each video data block EAV(0xFF00009D). Only data sent
between EAV and SAV is captured. Horizontal blanking and vertical blanking are ignored. Use of
the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the
interface, thereby reducing the pin count. In order to retrieve both frame and line synchronization
properly, at least one line of vertical blanking is mandatory.
FF
00
SAV
00
80
1 line
Y
Y
Cb
Cb
Y
Y
Figure 39-3
Cr
Cr
Y
Y
Active Video
Cb
Frame
Cb
Y
and
Cr
Y
Figure
Y
Cr
Y
Cb
Y
39-4.
Cr
Y
Y
Cr
Cb FF
00
EAV
AT91SAM9260
00
9D
679