at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 768
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at91sam9260-cj
Manufacturer Part Number
at91sam9260-cj
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet
1.AT91SAM9260-CJ.pdf
(790 pages)
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44.3.3.4
44.3.3.5
44.3.4
44.3.4.1
44.3.4.2
44.3.5
44.3.5.1
768
AT91SAM9260
SDRAM Controller
Serial Peripheral Interface (SPI)
Data Write Operation and number of bytes
Flag Reset is not correct in half duplex mode
SDCLK Clock active after reset
Mobile SDRAM device initialization constraint
Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0
A STOP command must be sent with a software timeout.
The Data Write operation with a number of bytes less than 12 is impossible.
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The
BLKLEN or BCNT field are used to specify the real count number.
In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be
incorrect.
These flags are reset correctly after a PDC channel enable.
Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the
PDC channel by writing PDC_TXTEN or PDC_RXTEN.
After a reset, the SDRAM clock is always active leading to over consumption in the pad.
The following sequence stops the SDRAM clock.
Using Mobile SDRAM devices that need to have their DQMx level HIGH during Mobile SDRAM
device initialization may lead to data bus contention and thus external memories on the same
EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “Don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
If the SPI is used in the following configuration:
1. Set the bit LPCB in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to
• master mode
• CPOL = 1 and NCPHA = 0
• multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR not equal to 1
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
complete.
6221G–ATARM–31-Jan-08
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