at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 775

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Table 44-1.
6221G–ATARM–31-Jan-08
Revision
6221F (cont.)
6221E
Current version appears first
Comments
Errata: Added ADC errata,
to
In
device initialization constraint” on page
In
Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and
NCPHA = 0” on page
In
“Unexpected RK clock cycle when RK outputs a clock during data transfer” on
page 787
transfer” on page
Added
Added
In
and Hardware Handshaking mod.” on page 789
Low” on page
All new information in
Masters,” on page 18
“AT91SAM9260 Masters to Slaves Access,” on page
In
NRD, NWR0, NWR1, NWR3.
Added details on Timer/Counter blocks in
38.
Updated Chip ID in
Removed information on Tightly-coupled Memories in
Processor Overview” on page
Boot Program: Updated
page 79
information.
In
83.
EBI: Updated signal names in
Interface” on page
Updated A21 and A22 signals in
Connections,” on page
Removed software recommendation for NANDOE and NANDWE PIO multiplexing
in
RSTC: Updated
POR output wave.
Updated
VDDCORE and backup_nreset signal reactivation.
Added new
SHDW: Corrected offset value for SHDW_SR register in
Controller (SHDWC) Registers,” on page
ECC: Corrected offset value for ECC_SR register in
Mapping,” on page
Section 20.7.3.2 “Software Configuration” on page
Section 44.2.1.11 ”ADC: Sleep Mode” on page
Section 44.2.7 ”SDRAM Controller” on page
Section 44.2.8 ”Serial Peripheral Interface (SPI)” on page
Section 44.2.9 ”Serial Synchronous Controller (SSC)” on page
Section 44.2.13 ”USART” on page
Figure 2-1 ”AT91SAM9260 Block Diagram” on page
Section 13.4 ”DataFlash
Section 44.2.9 “Static Memory Controller” on page
Section 44.2.11 ”Two-wire Interface (TWI)” on page
and
Section 14.3.4.1 “General Reset” on page 91
and
Section 14.3.3 “BMS Sampling” on page
Table 13-4, “Input Frequencies Supported,” on page 80
789.
“Incorrect first RK clock cycle when RK outputs a clock during data
Figure 14-4, ”General Reset State” on page 96
787.
140, A[20-18], NRD, NWR0, NWR1, NWR3, A21 and A22.
242.
Section 9.12 “Chip Identification” on page
786.
Section 7.2.1 ”Matrix
and
144.
Table 13-3, “Large Crystal Table (MHz) OSCSEL = 1,” on
Section 7.2.3 ”Master to Slave
Section 44.2.1.1 ”ADC: DRDY Bit Cleared” on page 782
Boot”, corrected
41. Not applicable to product.
Figure 20-1 ”Organization of the External Bus
Table 20-4, “EBI Pins and External Device
789, added
786.
127.
Section 10.4.5 “Timer Counter” on page
Masters”,
Figure 13-4 ”LDR Opcode” on page
786, updated
and
“TXD signal is floating in Modem
783.
“DCD is Active High instead of
Table 23-1, “Register
91.
Table 7-1, “List of Bus Matrix
18.
157.
Section 11. “ARM926EJ-S
with new information on
4, updated EBI signals
Table 18-2, “Shutdown
Access”,
762.
788.
786, added
“Mobile SDRAM
31.
with Main Supply
787, added
Table 7-3,
with new
“Bad
AT91SAM9260
Change Request Ref.
4718
4637
4769
4980
4691
4720
4457
4431
4369
4582
4402
4266
4451
4431
4375
4215
4250
4372
4224
775