at91sam9260-cj ATMEL Corporation, at91sam9260-cj Datasheet - Page 394

• Manufacturer Part Number: at91sam9260-cj
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

31.7.7
Figure 31-14. TWI Write Operation with Single Data Byte without Internal Address
394
AT91SAM9260
Read-write Flowcharts
The following flowcharts shown in
page
give examples for read and write operations. A polling or interrupt method can be used to check
the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be
configured first.
396,
Figure 31-17 on page
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Device slave address (DADR)
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
Write ==> bit MREAD = 0
TWI_THR = Data to send
Set the Control register:
Load Transmit register
- Transfer direction bit
Read Status register
Read Status register
(Needed only once)
Transfer finished
- Master enable
TXCOMP = 1?
Set TWI clock
TXRDY = 1?
Yes
Yes
BEGIN
397,
Figure
Figure 31-18 on page 398
31-14,
No
No
Figure 31-15 on page
and
Figure 31-19 on page 399
395,
6221G–ATARM–31-Jan-08
Figure 31-16 on