mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 147

• Manufacturer Part Number: mc9s12e256
• Description: Hcs12 Microcontrollers 16-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

3.3.5
Port S is associated with the serial peripheral interface (SPI) and serial communication interfaces (SCI0
and SCI1). Each pin is assigned to these modules according to the following priority: SPI/SCI1/SCI0 >
general-purpose I/O.
When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to
Chapter 9, “Serial Peripheral Interface (SPIV3)”
When the SCI1 receiver and transmitter are enabled, the PS[3:2] pins become TXD1 and RXD1
respectively. When the SCI0 receiver and transmitter are enabled, the PS[1:0] pins become TXD0 and
RXD0 respectively. Refer to
enabling and disabling the SCI receiver and transmitter.
During reset, port S pins are configured as high-impedance inputs.
3.3.5.1
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRSx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRSx) is set to 0 (input), a read returns the value of the pin.
3.3.5.2
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
Freescale Semiconductor
SCI1/SCI0:
Reset
Reset
SPI:
W
R
W
R
PTIS7
Port S
Port S I/O Register (PTS)
Port S Input Register (PTIS)
PTS7
u
7
SS
7
0
= Reserved or Unimplemented
PTIS6
PTS6
u
SCK
6
0
6
Chapter 8, “Serial Communication Interface (SCIV4)”
Figure 3-30. Port S Input Register (PTIS)
Figure 3-29. Port S I/O Register (PTS)
PTIS5
MC9S12E256 Data Sheet, Rev. 1.08
PTS5
MOSI
u
5
0
5
PTIS4
for information on enabling and disabling the SPI.
PTS4
MISO
u
4
0
4
u = Unaffected by reset
PTIS3
PTS3
TXD1
3
u
0
3
Chapter 3 Port Integration Module (PIM9E256V1)
PTIS2
PTS2
RXD1
u
2
0
2
PTIS1
for information on
PTS1
TXD0
u
1
0
1
PTIS0
PTS0
RXD0
u
0
0
0
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