mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 522

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mc9s12e256

Manufacturer Part Number
mc9s12e256
Description
Hcs12 Microcontrollers 16-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 18 Multiplexed External Bus Interface (MEBIV3)
18.3.2.7
Read: Anytime when register is in the map
Write: Anytime when register is in the map
Data direction register E is associated with port E. For bits in port E that are configured as general-purpose
I/O lines, DDRE determines the primary direction of each of these pins. A 1 causes the associated bit to
be an output and a 0 causes the associated bit to be an input. Port E bit 1 (associated with IRQ) and bit 0
(associated with XIRQ) cannot be configured as outputs. Port E, bits 1 and 0, can be read regardless of
whether the alternate interrupt function is enabled. The value in a DDR bit also affects the source of data
for reads of the corresponding PORTE register. If the DDR bit is 0 (input) the buffered pin input state is
read. If the DDR bit is 1 (output) the associated port data register bit state is read.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally. Also, it is not in the map in expanded modes while the EME control
bit is set.
522
Reset
DDRE
Field
7:2
W
R
Bit 7
Data Direction Port E
0 Configure the corresponding I/O pin as an input
1 Configure the corresponding I/O pin as an output
Note: It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from inputs to
Data Direction Register E (DDRE)
0
7
outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling
as outputs.
= Unimplemented or Reserved
6
0
6
Figure 18-12. Data Direction Register E (DDRE)
Table 18-5. DDRE Field Descriptions
MC9S12E256 Data Sheet, Rev. 1.08
5
0
5
4
0
4
Description
3
3
0
Bit 2
0
2
Freescale Semiconductor
0
0
1
0
0
0

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