mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 292

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mc9s12e256

Manufacturer Part Number
mc9s12e256
Description
Hcs12 Microcontrollers 16-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 9 Serial Peripheral Interface (SPIV3)
The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking
place. In the other cases, the divider is disabled to decrease I
9.4.5
9.4.5.1
The SS output feature automatically drives the SS pin low during transmission to select external devices
and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin
is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting SSOE and
MODFEN bit as shown in
The mode fault feature is disabled while SS output is enabled.
9.4.5.2
The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see
this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit
decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and
the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and
MOSI pin in slave mode are not used by the SPI.
292
Bidirectional Mode
When SPE = 1
Normal Mode
SPC0 = 0
SPC0 = 1
Special Features
SS Output
Bidirectional Mode (MOSI or MISO)
Care must be taken when using the SS output feature in a multimaster
system because the mode fault feature is not available for detecting system
errors between masters.
Serial Out
Serial Out
Table
BaudRateDivisor
Serial In
Serial In
SPI
SPI
Table 9-9. Normal Mode and Bidirectional Mode
Master Mode MSTR = 1
Figure 9-11. Baud Rate Divisor Equation
9-3.
MC9S12E256 Data Sheet, Rev. 1.08
BIDIROE
=
NOTE
SPPR
MOMI
MOSI
MISO
+
DD
1
current.
2
SPR
Serial Out
Serial Out
Serial In
Serial In
SPI
SPI
+
Slave Mode MSTR = 0
1
BIDIROE
Freescale Semiconductor
Table
MOSI
MISO
SISO
9-9). In

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