mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 195

• Manufacturer Part Number: mc9s12e256
• Description: Hcs12 Microcontrollers 16-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
CME
0
1
1
SCME
X
0
1
SCMIE
X
X
0
Clock failure -->
Clock failure -->
Clock Monitor failure -->
Scenario 1: OSCCLK recovers prior to exiting Pseudo-Stop Mode.
Scenario 2: OSCCLK does not recover prior to exiting Pseudo-Stop Mode.
Table 4-12. Outcome of Clock Loss in Pseudo-Stop Mode
No action, clock loss not detected.
CRG performs Clock Monitor Reset immediately
– MCU remains in Pseudo-Stop Mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start Clock Quality Check,
– Set SCMIF interrupt flag.
Some time later OSCCLK recovers.
– CM no longer indicates a failure,
– 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k.,
– SCM deactivated,
– PLL disabled,
– VREG disabled.
– MCU remains in Pseudo-Stop Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
– Exit Pseudo-Stop Mode using OSCCLK as system clock (SYSCLK),
– Continue normal operation.
– Exit Pseudo-Stop Mode using OSCCLK as system clock,
– Start reset sequence.
– MCU remains in Pseudo-Stop Mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start Clock Quality Check,
– Set SCMIF interrupt flag,
– Keep performing Clock Quality Checks (could continue infinitely)
Some time later either a wakeup interrupt occurs (no SCM interrupt)
– Exit Pseudo-Stop Mode in SCM using PLL clock (f
– Continue to perform additional Clock Quality Checks until OSCCLK
or an External RESET is applied.
– Exit Pseudo-Stop Mode in SCM using PLL clock (f
– Start reset sequence,
– Continue to perform additional Clock Quality Checks until OSCCLK
or an External Reset is applied.
is o.k. again.
is o.k.again.
while in Pseudo-Stop Mode.
MC9S12E256 Data Sheet, Rev. 1.08
CRG Actions
Chapter 4 Clocks and Reset Generator (CRGV4)
SCM
SCM
) as system clock
) as system clock
195