mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 148

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mc9s12e256

Manufacturer Part Number
mc9s12e256
Description
Hcs12 Microcontrollers 16-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 3 Port Integration Module (PIM9E256V1)
3.3.5.3
Read: Anytime. Write: Anytime.
This register configures port pins PS[7:4] and PS[2:0] as either input or output.
When the SPI is enabled, the PS[7:4] pins become the SPI bidirectional pins. The associated Data
Direction Register bits have no effect.
When the SCI1 transmitter is enabled, the PS[3] pin becomes the TXD1 output pin and the associated Data
Direction Register bit has no effect. When the SCI1 receiver is enabled, the PS[2] pin becomes the RXD1
input pin and the associated Data Direction Register bit has no effect.
When the SCI0 transmitter is enabled, the PS[1] pin becomes the TXD0 output pin and the associated Data
Direction Register bit has no effect. When the SCI0 receiver is enabled, the PS[0] pin becomes the RXD0
input pin and the associated Data Direction Register bit has no effect.
If the SPI, SCI1 and SCI0 functions are disabled, the corresponding Data Direction Register bit reverts to
control the I/O direction of the associated pin.
148
DDRS[7:0]
Reset
Field
7:0
W
R
DDRS7
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port S Data Direction Register (DDRS)
0
7
DDRS6
0
6
Figure 3-31. Port S Data Direction Register (DDRS)
Table 3-22. DDRS Field Descriptions
DDRS5
MC9S12E256 Data Sheet, Rev. 1.08
0
5
DDRS4
0
4
Description
DDRS3
3
0
DDRS2
0
2
DDRS1
Freescale Semiconductor
0
1
DDRS0
0
0

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