mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 389

• Manufacturer Part Number: mc9s12e256
• Description: Hcs12 Microcontrollers 16-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Reference
PWM function.
Freescale Semiconductor
CON45
CON23
CON01
PSWAI
PFRZ
Field
6
5
4
3
2
Section 12.4.2.7, “PWM 16-Bit Functions,”
Concatenate Channels 4 and 5
0 Channels 4 and 5 are separate 8-bit PWMs.
1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high-order
Concatenate Channels 2 and 3
0 Channels 2 and 3 are separate 8-bit PWMs.
1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high-order
Concatenate Channels 0 and 1
0 Channels 0 and 1 are separate 8-bit PWMs.
1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high-order
PWM Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling the
input clock to the prescaler.
0 Allow the clock to the prescaler to continue while in wait mode.
1 Stop the input clock to the prescaler whenever the MCU is in wait mode.
PWM Counters Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the
prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode
the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function
to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that after normal
program flow is continued, the counters are re-enabled to simulate real-time operations. Because the registers
remain accessible in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode.
0 Allow PWM to continue while in freeze mode.
1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation.
byte and channel 5 becomes the low-order byte. Channel 5 output pin is used as the output for this 16-bit PWM
(bit 5 of port PWMP). Channel 5 clock select control bit determines the clock source, channel 5 polarity bit
determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit
determines the output mode.
byte and channel 3 becomes the low-order byte. Channel 3 output pin is used as the output for this 16-bit PWM
(bit 3 of port PWMP). Channel 3 clock select control bit determines the clock source, channel 3 polarity bit
determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit
determines the output mode.
byte and channel 1 becomes the low-order byte. Channel 1 output pin is used as the output for this 16-bit PWM
(bit 1 of port PWMP). Channel 1 clock select control bit determines the clock source, channel 1 polarity bit
determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit
determines the output mode.
Change these bits only when both corresponding channels are disabled.
Table 12-9. PWMCTL Field Descriptions
MC9S12E256 Data Sheet, Rev. 1.08
NOTE
Description
for a more detailed description of the concatenation
Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
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