mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 445

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mc9s12e256

Manufacturer Part Number
mc9s12e256
Description
Hcs12 Microcontrollers 16-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 15
Background Debug Module (BDMV4)
15.1
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12
core platform.
A block diagram of the BDM is shown in
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
BDMV4 has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to show the clock rate and a handshake
signal to indicate when an operation is complete. The system is backwards compatible with older external
interfaces.
Freescale Semiconductor
Introduction
SYSTEM
HOST
BDMACT
ENBDM
ENTAG
TRACE
SDV
BKGD
16-BIT SHIFT REGISTER
INSTRUCTION DECODE
Figure 15-1. BDM Block Diagram
MC9S12E256 Data Sheet, Rev. 1.08
AND EXECUTION
STANDARD BDM
LOOKUP TABLE
FIRMWARE
Figure
15-1.
CONTROL LOGIC
BUS INTERFACE
CLKSW
AND
ADDRESS
DATA
CLOCKS
445

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