mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 502

no-image

mc9s12e256

Manufacturer Part Number
mc9s12e256
Description
Hcs12 Microcontrollers 16-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc9s12e256CFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12e256CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
mc9s12e256CPVE
Manufacturer:
FREESCA
Quantity:
300
Part Number:
mc9s12e256CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12e256MFUE
Manufacturer:
FREESCAL
Quantity:
329
Part Number:
mc9s12e256MFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12e256MPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12e256VFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 17 Interrupt (INTV1)
The interrupt sub-block decodes the priority of all system exception requests and provides the applicable
vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a
non-maskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background
debug mode request, and three system reset vector requests. All interrupt related exception requests are
managed by the interrupt sub-block (INT).
17.1.1
The INT includes these features:
17.1.2
The functionality of the INT sub-block in various modes of operation is discussed in the subsections that
follow.
502
Provides two to 122 I-bit maskable interrupt vectors (0xFF00–0xFFF2)
Provides one X-bit maskable interrupt vector (0xFFF4)
Provides a non-maskable software interrupt (SWI) or background debug mode request vector
(0xFFF6)
Provides a non-maskable unimplemented opcode trap (TRAP) vector (0xFFF8)
Provides three system reset vectors (0xFFFA–0xFFFE) (reset, CMR, and COP)
Determines the appropriate vector and drives it onto the address bus at the appropriate time
Signals the CPU that interrupts are pending
Provides control registers which allow testing of interrupts
Provides additional input signals which prevents requests for servicing I and X interrupts
Wakes the system from stop or wait mode when an appropriate interrupt occurs or whenever XIRQ
is active, even if XIRQ is masked
Provides asynchronous path for all I and X interrupts, (0xFF00–0xFFF4)
(Optional) selects and stores the highest priority I interrupt based on the value written into the
HPRIO register
Normal operation
The INT operates the same in all normal modes of operation.
Special operation
Interrupts may be tested in special modes through the use of the interrupt test registers.
Emulation modes
The INT operates the same in emulation modes as in normal modes.
Low power modes
See
Section 17.4.1, “Low-Power
Features
Modes of Operation
MC9S12E256 Data Sheet, Rev. 1.08
Modes,” for details
Freescale Semiconductor

Related parts for mc9s12e256