kfm2g16q2m-deb8 Samsung Semiconductor, Inc., kfm2g16q2m-deb8 Datasheet
kfm2g16q2m-deb8
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kfm2g16q2m-deb8 Summary of contents
Page 1
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) KFM2G16Q2M KFN4G16Q2M KFK8G16Q2M 2Gb MuxOneNAND M-die INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Revision History Document Title MuxOneNAND Revision History Revision No. History 0.0 1. Initial issue. 0.1 1. Corrected errata. 2. Changed a tem from MAT to Plane. 3. Chapter 1.4 & 2.3 & 8.0 : Revised the package size from 11x13 to 10x13. 4. Chapter 2.8.3 : Eliminated ’Top boot’ option. 5. Chapter 2.8.12 & 2.8.16 & 3.8 : Added a. comment about FSA & FCSA setting on Cache Read Operation 6 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Revision History Document Title MuxOneNAND Revision History Revision No. History 1.1 11. Chapter 3.11.3 2X Interleave Cache Program Operation Flow Diagram updated. 12. Chapter 3.13.2 Multi-Block Erase Operation Case 3 updated. 13. Chapter 3.14 OTP, 1st OTP, OTP&1st block OTP Flow chart updated. 14. Chapter 3.14.3 OTP Block Lock Operation corrected errata. ...
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... Section 2.0 describes the MuxOneNAND device. Section 3.0 provides information about device operation. Electrical specifications and timing waveforms are in Sections 4.0 through 6.0. Section 7.0 provides additional application and technical notes pertaining to use of the MuxOneNAND. Package dimensions are found in Section 8.0 Density Part No. 2Gb KFM2G16Q2M-DEBx 4Gb KFN4G16Q2M-DEBx 8Gb KFK8G16Q2M-DEBx 1.1 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 1.2 Ordering Information Samsung OneNAND Memory Device Type M : Mux Single Chip N : Mux Dual Chip K: Mux Quad Chip Density 2G : 2Gb 4G : 4Gb 8G : 8Gb Organization x16 Organization Operating Voltage Range Q : 1.8V(1 1.95V) 1.3 Architectural Benefits MuxOneNAND is a highly integrated non-volatile memory solution based around a NAND Flash memory array. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 1.4 Product Features Device Architecture • Design Technology: • Supply Voltage: • Host Interface: • 5KB Internal BufferRAM: • SLC NAND Array: Device Performance • Host Interface Type: • Programmable Burst Read Latency: • Multiple Sector Read/Write: • Multiple Reset Modes: • ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 1.5 General Overview ™ MuxOneNAND ‚ monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This device includes con- trol logic, a NAND Flash array, and 5KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering (BootRAM) and 4KB for data buffering (DataRAM), split between 2 independent buffers ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.0 DEVICE DESCRIPTION 2.1 Detailed Product Description The MuxOneNAND is an advanced generation, high-performance NAND-based Flash memory. It integrates on-chip a single-level-cell (SLC) NAND Flash Array memory with two independent data buffers, boot RAM buffer, a page buffer for the Flash array, and a one-time-programmable block. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.2 Definitions B (capital letter) W (capital letter) b (lower-case letter) ECC Calculated ECC Written ECC BufferRAM BootRAM DataRAM Sector Possible data unit to be read from memory to BufferRAM programmed to memory. Data unit Byte, 8bits Word, 16bits Bit Error Correction Code ECC that has been calculated during a load or program access ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.3 Pin Configuration 2.3.1 2Gb Product (KFM2G16Q2M 63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA ADQ1 SS SS ADQ2 V CC ADQ3 ADQ7 ADQ14 OE ADQ6 Core V CC ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 IO NC ADQ0 NC ADQ15 ADQ10 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.3.2 4Gb Product (KFN4G16Q2M 63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA ADQ1 SS SS ADQ2 V CC ADQ3 ADQ7 ADQ14 OE ADQ6 Core V CC ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 IO NC ADQ0 NC ADQ15 ADQ10 ADQ9 CLK ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.3.3 8Gb Product (KFK8G16Q2M 63ball, 10mm x 13mm x max 1.4mmt , 0.8mm ball pitch FBGA ADQ1 SS SS ADQ2 V CC ADQ3 ADQ7 ADQ14 OE ADQ6 Core V CC ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 IO NC ADQ0 NC ADQ15 ADQ10 ADQ9 INT2 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.4 Pin Description Pin Name Type Host Interface Multiplexed Address/Data bus - Inputs for addresses during read operation, which are for addressing BufferRAM & Register. ADQ15~ADQ0 I/O - Inputs data during program and commands for all operations, outputs data during memory array/ register read cycles ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.5 Block Diagram ADQ15~ADQ0 CLK CE / CE1 CE2 AVD INT / INT1 INT2* RDY * Note : CE2 and INT2 are only available in QDP device 2.6 Memory Array Organization The MuxOneNAND architecture integrates several memory areas on a single chip. 2.6.1 Internal (NAND Array) Memory Organization The on-chip internal memory is a single-level-cell (SLC) NAND array used for data storage and code ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Internal Memory Array Information Area Main Spare Internal Memory Array Organization Main Area Main Area 512B Sector0 512B Sector1 Main Area 2KB Page0 2KB Page63 Block Page 128KB 2KB 4KB 64B Sector 512B Page 512B Sector3 512B Sector2 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.6.2 External (BufferRAM) Memory Organization The on-chip external memory is comprised of 3 buffers used for Boot Code storage and data buffering. The BootRAM is a 1KB buffer that receives Boot Code from the internal memory and makes it available to the host at start up. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) External Memory Array Organization BootRAM DataRAM0 DataRAM1 FLASH MEMORY Main area data Spare area data (512B) (16B) BootRAM 0 BootRAM 1 DataRAM 0_0 DataRAM 0_1 DataRAM 0_2 DataRAM 0_3 DataRAM 1_0 DataRAM 1_1 DataRAM 1_2 DataRAM 1_3 17 Sector: (512 + 16) Byte ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.7 Memory Map The following tables are the memory maps for the MuxOneNAND. 2.7.1 Internal (NAND Array) Memory Organization The following tables show the Internal Memory address map in word order. Page and Sector Block Block Address Address Block0 0000h 0000h~00FFh ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block64 0040h 0000h~00FFh Block65 0041h 0000h~00FFh Block66 0042h 0000h~00FFh Block67 0043h 0000h~00FFh Block68 0044h 0000h~00FFh Block69 0045h 0000h~00FFh Block70 0046h 0000h~00FFh Block71 0047h 0000h~00FFh Block72 0048h 0000h~00FFh Block73 0049h 0000h~00FFh Block74 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block128 0080h 0000h~00FFh Block129 0081h 0000h~00FFh Block130 0082h 0000h~00FFh Block131 0083h 0000h~00FFh Block132 0084h 0000h~00FFh Block133 0085h 0000h~00FFh Block134 0086h 0000h~00FFh Block135 0087h 0000h~00FFh Block136 0088h 0000h~00FFh Block137 0089h 0000h~00FFh Block138 ...
Page 21
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block192 00C0h 0000h~00FFh Block193 00C1h 0000h~00FFh Block194 00C2h 0000h~00FFh Block195 00C3h 0000h~00FFh Block196 00C4h 0000h~00FFh Block197 00C5h 0000h~00FFh Block198 00C6h 0000h~00FFh Block199 00C7h 0000h~00FFh Block200 00C8h 0000h~00FFh Block201 00C9h 0000h~00FFh Block202 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block256 0100h 0000h~00FFh Block257 0101h 0000h~00FFh Block258 0102h 0000h~00FFh Block259 0103h 0000h~00FFh Block260 0104h 0000h~00FFh Block261 0105h 0000h~00FFh Block262 0106h 0000h~00FFh Block263 0107h 0000h~00FFh Block264 0108h 0000h~00FFh Block265 0109h 0000h~00FFh Block266 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block320 0140h 0000h~00FFh Block321 0141h 0000h~00FFh Block322 0142h 0000h~00FFh Block323 0143h 0000h~00FFh Block324 0144h 0000h~00FFh Block325 0145h 0000h~00FFh Block326 0146h 0000h~00FFh Block327 0147h 0000h~00FFh Block328 0148h 0000h~00FFh Block329 0149h 0000h~00FFh Block330 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block384 0180h 0000h~00FFh Block385 0181h 0000h~00FFh Block386 0182h 0000h~00FFh Block387 0183h 0000h~00FFh Block388 0184h 0000h~00FFh Block389 0185h 0000h~00FFh Block390 0186h 0000h~00FFh Block391 0187h 0000h~00FFh Block392 0188h 0000h~00FFh Block393 0189h 0000h~00FFh Block394 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block448 01C0h 0000h~00FFh Block449 01C1h 0000h~00FFh Block450 01C2h 0000h~00FFh Block451 01C3h 0000h~00FFh Block452 01C4h 0000h~00FFh Block453 01C5h 0000h~00FFh Block454 01C6h 0000h~00FFh Block455 01C7h 0000h~00FFh Block456 01C8h 0000h~00FFh Block457 01C9h 0000h~00FFh Block458 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block512 0200h 0000h~00FFh Block513 0201h 0000h~00FFh Block514 0202h 0000h~00FFh Block515 0203h 0000h~00FFh Block516 0204h 0000h~00FFh Block517 0205h 0000h~00FFh Block518 0206h 0000h~00FFh Block519 0207h 0000h~00FFh Block520 0208h 0000h~00FFh Block521 0209h 0000h~00FFh Block522 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block576 0240h 0000h~00FFh Block577 0241h 0000h~00FFh Block578 0242h 0000h~00FFh Block579 0243h 0000h~00FFh Block580 0244h 0000h~00FFh Block581 0245h 0000h~00FFh Block582 0246h 0000h~00FFh Block583 0247h 0000h~00FFh Block584 0248h 0000h~00FFh Block585 0249h 0000h~00FFh Block586 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block640 0280h 0000h~00FFh Block641 0281h 0000h~00FFh Block642 0282h 0000h~00FFh Block643 0283h 0000h~00FFh Block644 0284h 0000h~00FFh Block645 0285h 0000h~00FFh Block646 0286h 0000h~00FFh Block647 0287h 0000h~00FFh Block648 0288h 0000h~00FFh Block649 0289h 0000h~00FFh Block650 ...
Page 29
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block704 02C0h 0000h~00FFh Block705 02C1h 0000h~00FFh Block706 02C2h 0000h~00FFh Block707 02C3h 0000h~00FFh Block708 02C4h 0000h~00FFh Block709 02C5h 0000h~00FFh Block710 02C6h 0000h~00FFh Block711 02C7h 0000h~00FFh Block712 02C8h 0000h~00FFh Block713 02C9h 0000h~00FFh Block714 ...
Page 30
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block768 0300h 0000h~00FFh Block769 0301h 0000h~00FFh Block770 0302h 0000h~00FFh Block771 0303h 0000h~00FFh Block772 0304h 0000h~00FFh Block773 0305h 0000h~00FFh Block774 0306h 0000h~00FFh Block775 0307h 0000h~00FFh Block776 0308h 0000h~00FFh Block777 0309h 0000h~00FFh Block778 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block832 0340h 0000h~00FFh Block833 0341h 0000h~00FFh Block834 0342h 0000h~00FFh Block835 0343h 0000h~00FFh Block836 0344h 0000h~00FFh Block837 0345h 0000h~00FFh Block838 0346h 0000h~00FFh Block839 0347h 0000h~00FFh Block840 0348h 0000h~00FFh Block841 0349h 0000h~00FFh Block842 ...
Page 32
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block896 0380h 0000h~00FFh Block897 0381h 0000h~00FFh Block898 0382h 0000h~00FFh Block899 0383h 0000h~00FFh Block900 0384h 0000h~00FFh Block901 0385h 0000h~00FFh Block902 0386h 0000h~00FFh Block903 0387h 0000h~00FFh Block904 0388h 0000h~00FFh Block905 0389h 0000h~00FFh Block906 ...
Page 33
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block960 03C0h 0000h~00FFh Block961 03C1h 0000h~00FFh Block962 03C2h 0000h~00FFh Block963 03C3h 0000h~00FFh Block964 03C4h 0000h~00FFh Block965 03C5h 0000h~00FFh Block966 03C6h 0000h~00FFh Block967 03C7h 0000h~00FFh Block968 03C8h 0000h~00FFh Block969 03C9h 0000h~00FFh Block970 ...
Page 34
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1024 0400h 0000h~00FFh Block1025 0401h 0000h~00FFh Block1026 0402h 0000h~00FFh Block1027 0403h 0000h~00FFh Block1028 0404h 0000h~00FFh Block1029 0405h 0000h~00FFh Block1030 0406h 0000h~00FFh Block1031 0407h 0000h~00FFh Block1032 0408h 0000h~00FFh Block1033 0409h 0000h~00FFh Block1034 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1088 0440h 0000h~00FFh Block1089 0441h 0000h~00FFh Block1090 0442h 0000h~00FFh Block1091 0443h 0000h~00FFh Block1092 0444h 0000h~00FFh Block1093 0445h 0000h~00FFh Block1094 0446h 0000h~00FFh Block1095 0447h 0000h~00FFh Block1096 0448h 0000h~00FFh Block1097 0449h 0000h~00FFh Block1098 ...
Page 36
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1152 0480h 0000h~00FFh Block1153 0481h 0000h~00FFh Block1154 0482h 0000h~00FFh Block1155 0483h 0000h~00FFh Block1156 0484h 0000h~00FFh Block1157 0485h 0000h~00FFh Block1158 0486h 0000h~00FFh Block1159 0487h 0000h~00FFh Block1160 0488h 0000h~00FFh Block1161 0489h 0000h~00FFh Block1162 ...
Page 37
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1216 04C0h 0000h~00FFh Block1217 04C1h 0000h~00FFh Block1218 04C2h 0000h~00FFh Block1219 04C3h 0000h~00FFh Block1220 04C4h 0000h~00FFh Block1221 04C5h 0000h~00FFh Block1222 04C6h 0000h~00FFh Block1223 04C7h 0000h~00FFh Block1224 04C8h 0000h~00FFh Block1225 04C9h 0000h~00FFh Block1226 ...
Page 38
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1280 0500h 0000h~00FFh Block1281 0501h 0000h~00FFh Block1282 0502h 0000h~00FFh Block1283 0503h 0000h~00FFh Block1284 0504h 0000h~00FFh Block1285 0505h 0000h~00FFh Block1286 0506h 0000h~00FFh Block1287 0507h 0000h~00FFh Block1288 0508h 0000h~00FFh Block1289 0509h 0000h~00FFh Block1290 ...
Page 39
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1344 0540h 0000h~00FFh Block1345 0541h 0000h~00FFh Block1346 0542h 0000h~00FFh Block1347 0543h 0000h~00FFh Block1348 0544h 0000h~00FFh Block1349 0545h 0000h~00FFh Block1350 0546h 0000h~00FFh Block1351 0547h 0000h~00FFh Block1352 0548h 0000h~00FFh Block1353 0549h 0000h~00FFh Block1354 ...
Page 40
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1408 0580h 0000h~00FFh Block1409 0581h 0000h~00FFh Block1410 0582h 0000h~00FFh Block1411 0583h 0000h~00FFh Block1412 0584h 0000h~00FFh Block1413 0585h 0000h~00FFh Block1414 0586h 0000h~00FFh Block1415 0587h 0000h~00FFh Block1416 0588h 0000h~00FFh Block1417 0589h 0000h~00FFh Block1418 ...
Page 41
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1472 05C0h 0000h~00FFh Block1473 05C1h 0000h~00FFh Block1474 05C2h 0000h~00FFh Block1475 05C3h 0000h~00FFh Block1476 05C4h 0000h~00FFh Block1477 05C5h 0000h~00FFh Block1478 05C6h 0000h~00FFh Block1479 05C7h 0000h~00FFh Block1480 05C8h 0000h~00FFh Block1481 05C9h 0000h~00FFh Block1482 ...
Page 42
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1536 0600h 0000h~00FFh Block1537 0601h 0000h~00FFh Block1538 0602h 0000h~00FFh Block1539 0603h 0000h~00FFh Block1540 0604h 0000h~00FFh Block1541 0605h 0000h~00FFh Block1542 0606h 0000h~00FFh Block1543 0607h 0000h~00FFh Block1544 0608h 0000h~00FFh Block1545 0609h 0000h~00FFh Block1546 ...
Page 43
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1600 0640h 0000h~00FFh Block1601 0641h 0000h~00FFh Block1602 0642h 0000h~00FFh Block1603 0643h 0000h~00FFh Block1604 0644h 0000h~00FFh Block1605 0645h 0000h~00FFh Block1606 0646h 0000h~00FFh Block1607 0647h 0000h~00FFh Block1608 0648h 0000h~00FFh Block1609 0649h 0000h~00FFh Block1610 ...
Page 44
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1664 0680h 0000h~00FFh Block1665 0681h 0000h~00FFh Block1666 0682h 0000h~00FFh Block1667 0683h 0000h~00FFh Block1668 0684h 0000h~00FFh Block1669 0685h 0000h~00FFh Block1670 0686h 0000h~00FFh Block1671 0687h 0000h~00FFh Block1672 0688h 0000h~00FFh Block1673 0689h 0000h~00FFh Block1674 ...
Page 45
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1728 06C0h 0000h~00FFh Block1729 06C1h 0000h~00FFh Block1730 06C2h 0000h~00FFh Block1731 06C3h 0000h~00FFh Block1732 06C4h 0000h~00FFh Block1733 06C5h 0000h~00FFh Block1734 06C6h 0000h~00FFh Block1735 06C7h 0000h~00FFh Block1736 06C8h 0000h~00FFh Block1737 06C9h 0000h~00FFh Block1738 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1792 0700h 0000h~00FFh Block1793 0701h 0000h~00FFh Block1794 0702h 0000h~00FFh Block1795 0703h 0000h~00FFh Block1796 0704h 0000h~00FFh Block1797 0705h 0000h~00FFh Block1798 0706h 0000h~00FFh Block1799 0707h 0000h~00FFh Block1800 0708h 0000h~00FFh Block1801 0709h 0000h~00FFh Block1802 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1856 0740h 0000h~00FFh Block1857 0741h 0000h~00FFh Block1858 0742h 0000h~00FFh Block1859 0743h 0000h~00FFh Block1860 0744h 0000h~00FFh Block1861 0745h 0000h~00FFh Block1862 0746h 0000h~00FFh Block1863 0747h 0000h~00FFh Block1864 0748h 0000h~00FFh Block1865 0749h 0000h~00FFh Block1866 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1920 0780h 0000h~00FFh Block1921 0781h 0000h~00FFh Block1922 0782h 0000h~00FFh Block1923 0783h 0000h~00FFh Block1924 0784h 0000h~00FFh Block1925 0785h 0000h~00FFh Block1926 0786h 0000h~00FFh Block1927 0787h 0000h~00FFh Block1928 0788h 0000h~00FFh Block1929 0789h 0000h~00FFh Block1930 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Page and Sector Block Block Address Address Block1984 07C0h 0000h~00FFh Block1985 07C1h 0000h~00FFh Block1986 07C2h 0000h~00FFh Block1987 07C3h 0000h~00FFh Block1988 07C4h 0000h~00FFh Block1989 07C85h 0000h~00FFh Block1990 07C6h 0000h~00FFh Block1991 07C7h 0000h~00FFh Block1992 07C8h 0000h~00FFh Block1993 07C9h 0000h~00FFh Block1994 ...
Page 50
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.7.2 Internal Memory Spare Area Assignment The figure below shows the assignment of the spare area in the Internal Memory NAND Array. Main area Main area 256W 256W Note1 Note1 Note2 Note2 Note2 Note3 Note3 Note3 LSB MSB LSB MSB LSB ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.7.3 External Memory (BufferRAM) Address Map The following table shows the External Memory address map in Word and Byte Order. Note that the data output is unknown while host reads a register bit of reserved area. Address Address Division (word order) (byte order) ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.7.4 External Memory Map Detail Information The tables below show Word Order Address Map information for the BootRAM and DataRAM main and spare areas. • BootRAM(Main area) -0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB 0000h~00FFh(512B) BootM 0 (sector 0 of page 0) • ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.7.5 External Memory Spare Area Assignment Word Byte Buf. F Address Address BootS 0 8000h 10000h 8001h 10002h 8002h 10004h 8003h 10006h 8004h 10008h ECC Code for Main area data (2 8005h 1000Ah ECC Code for Spare area data (1 8006h 1000Ch FFh(Reserved for the future use) ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Word Byte Buf. F Address Address DataS 0_2 8020h 10040h 8021h 10042h 8022h 10044h 8023h 10046h 8024h 10048h ECC Code for Main area data (2 8025h 1004Ah ECC Code for Spare area data (1 8026h 1004Ch 8027h 1004Eh DataS 0_3 8028h ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Word Byte Buf. F Address Address DataS 1_3 8048h 10090h 8049h 10092h 804Ah 10094h 804Bh 10096h 804Ch 10098h ECC Code for Main area data (2 804Dh 1009Ah ECC Code for Spare area data (1 804Eh 1009Ch 804Fh 1009Eh NOTE: - BI: Bad block Information > ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8 Registers Section 2.8 of this specification provides information about the MuxOneNAND registers. 2.8.1 Register Address Map This map describes the register addresses, register name, register description, and host accessibility. Address Address (word order) (byte order) F000h 1E000h F001h 1E002h F002h 1E004h ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Address Address (word order) (byte order) F24Dh 1E49Ah F24Eh 1E49Ch F24Fh~FEFFh 1E49Eh~1FDFEh FF00h 1FE00h FF01h 1FE02h FF02h 1FE04h FF03h 1FE06h FF04h 1FE08h FF05h 1FE0Ah FF06h 1FE0Ch FF07h 1FE0Eh FF08h 1FE10h FF09h~FFFFh 1FE12h~1FFFEh 2.8.2 Manufacturer ID Register F000h (R) This Read register describes the manufacturer's identification. ...
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... Register information DeviceID [1:0] Vcc DeviceID [2] Muxed/Demuxed DeviceID [3] Single/DDP DeviceID [7:4] Density 0000 = 128Mb, 0001 = 256Mb, 0010 = 512Mb, 0011 = 1Gb, 0100 = 2Gb, 0101=4Gb DeviceID [8] Bottom Boot Device ID Default Device KFM2G16Q2M KFN4G16Q2M KFK8G16Q2M Note1) Due to KFK8G16Q2M is QDP with dual KFN4G16Q2M, Device ID[15:0] is same as KFN4G16Q2M ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.4 Version ID Register F002h This Register is reserved for future use. 2.8.5 Data Buffer Size Register F003h (R) This Read register describes the size of the Data Buffer. F003h, default = 0800h Data Buffer Size Information Register information DataBufSize DataBufSize ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.6 Boot Buffer Size Register F004h (R) This Read register describes the size of the Boot Buffer. F004h, default = 0200h Register Information BootBufSize 2.8.7 Number of Buffers Register F005h (R) This Read register describes the number of each Buffer. F005h, default = 0201h 15 14 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.9 Start Address1 Register F100h (R/W) This Read/Write register describes the NAND Flash block address which will be loaded, programmed, or erased. F100h, default = 0000h DFS Reserved(0000) Note 1) Bit 0 should be fixed ’low’ Program and 2X Cache Program. Device 2Gb ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.11 Start Address3 Register F102h (R/W) This Read/Write register describes the NAND Flash destination block address which will be copy back programmed. Also, this regis- ter indicates the block address for the first page to be read in Cache Read Operation. F102h, default = 0000h ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.13 Start Address5 Register F104h (R/W) This Read/Write register describes the number of page in Synchronous Burst Block Read. F104h, default = 0000h Reserved(0000000000) Flash Page Count (FPC) Information FPC 000000 (Default) 000011 000100 .. 111111 Note) Synchronous Burst Block Read are NOT able to be perforformed with 1 or 2pages. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.17 Start Buffer Register F200h (R/W) This Read/Write register describes the BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA). The BufferRAM Sector Count (BSC) field specifies the number of sectors to be loaded, programmed, or copy back programmed value (the default value), the number of sector is "4". If the internal RAM buffer reaches its maximum value of 11, it will count value to meet the BSC value. For example, if BSA = 1101, BSC = 00, then the selected BufferRAM will count up from '1101 → ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.18 Command Register F220h (R/W) Command can be issued by two following methods, and user may select one way or the other to issue appropriate command; 1. Write command into Command Register when INT is at ready state. INT will automatically turn to busy state as command is issued. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.18.1 Two Methods to Clear Interrupt Register in Command Input To clear Interrupt Register in command input, user may select one from either following methods. First method is to turn INT low by manually writing 0000h to INT bit of Interrupt Register. Second method is input command while INT is high, and the device will automatically turn INT to low. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.19 System Configuration 1 Register F221h (R, R/W) This Read/Write register describes the system configuration. F221h, default = 40C0h R/W R/W R/W RM BRWL Read Mode (RM Read Mode Information[15] Item RM Burst Read Write Latency (BRWL) BRWL 000~010 011 3(up to 40MHz. min) 100 (default) ...
Page 68
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Burst Length (BL) Hosts must follow burst length set by BL when reading data in synchronous burst read. BL 000 001 010 011 100 101 110~111 Note 1) For normal synchronous burst read, setting BL=000 (continuous) will read 1K words, depending on the number of clocks. In using Synchronous Burst Block Read, setting BL=000 (continuous) will read the amount of data in a block set by number of page register ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) I/O Buffer Enable (IOBE) IOBE is the I/O Buffer Enable for the INT and RDY signals. At startup, INT and RDY outputs are High-Z. Bits 6 and 7 become valid after IOBE is set to "1". IOBE can be reset by a Cold Reset or by writing "0" to bit 5 of System Configuration1 Register. ...
Page 70
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Write Mode (WM Write Mode Information[1] Item WM MRS(Mode register Setting) Description The other Case Note) 1. Operation not guaranteed for cases not defined in above table. Boot Buffer Write Protect Status(BWPS) Boot Buffer Write Protect Status Information[0] ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.20 System Configuration 2 Register F222h This register is reserved for future use. 2.8.21 Controller Status Register F240h (R) This Read register shows the overall internal status of the MuxOneNAND and the controller. F240h, default = 0000h OnGo Lock Load Prog Erase Error OnGo This bit shows the overall internal status of the MuxOneNAND device ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Program This bit shows the Program Operation status Cache Program Operation, ’Prog’ bit shows the overall status of 2X Cache Program process. Program Information[12] Item Prog Program Operation status Erase This bit shows the Erase Operation status. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Reset / Busy (RSTB) This bit shows the Reset Operation status. RSTB Information[7] Item RSTB OTP Lock Status (OTP ) L This bit shows whether the OTP block is locked or unlocked. Locking the OTP has the effect of a 'write-protect' to guard against accidental re-programming of data stored in the OTP block. ...
Page 74
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Plane1 Current This bit shows the current program status of Plane1 at Final 2X Cache Program, 2X Program, and 2X Interleave Cache Program. During 2X Cache Program prior to ’2X Program’ command, which will be Final 2X Cache Program, this bit will be invalid (fixed to 0). Plane1 Current Information[3] ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Controller Status Register Output Modes [15] [14] [13] Mode OnGo Lock Load Load / Cache Read Ongoing Program Ongoing Erase Ongoing Reset Ongoing Multi-Block Erase Ongoing Erase Verify Read Ongoing Load / Cache Read Program OK ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Controller Status Register Output Modes (Continued) [15] [14] [13] Mode OnGo Lock Load Program Fail on 2X Program (Plane1) Program Fail on 2X Program (Plane2) Program Fail on 2X Program (Plane1 & Plane2) Previous Program Fail During 2X Cache Program ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.22 Interrupt Status Register F241h (R/W) This Read/Write register shows status of the MuxOneNAND interrupts. In DDP, INT register will not be written if DFS is not set. F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset INT Reserved(0000000) Interrupt (INT) This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes low if INTpol is high and goes high if INTpol is low ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Write Interrupt (WI) This is the Write interrupt bit. WI Interrupt [6] Status Conditions At the completion of an Program Operation sets itself to ’1’ (0080h, 001Ah, 001Bh, 007Dh, 007Fh) ’0’ is written to this bit, Cold/Warm/Hot reset is being performed, or clears to ’0’ command is written to Command Register in ...
Page 79
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.23 Start Block Address Register F24Ch (R/W) This Read/Write register shows the NAND Flash block address in the Write Protection mode. Setting this register precedes a 'Lock Block' command, 'Unlock Block' command, or ’Lock-Tight' Command. F24Ch, default = 0000h Reserved(000000) Device 2Gb ...
Page 80
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.26 ECC Status Register FF00h (R) This Read register shows the Error Correction Status. The MuxOneNAND can detect 1- or 2-bit errors and correct 1-bit errors. 3-bit or more error detection and correction is not supported. ECC can be performed on the NAND Flash main and spare memory areas. The ECC status register can also show the number of errors in a sector as a result of an ECC check in during a load operation ...
Page 81
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.27 ECC Result of 1 Register FF01h (R) This Read register shows the Error Correction result for the 1st selected sector of the main area data. ECCposWord0 is the error position address in the Main Area data of 256 words. ECCposIO0 is the error position address which selects DQs. ...
Page 82
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2.8.31 ECC Result of 3 Register FF05h (R) This Read register shows the Error Correction result for the 3rd selected sector of the main area data. ECCposWord2 is the error position address in the Main Area data of 256 words. ECCposIO2 is the error position address which selects DQs. ...
Page 83
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) ECC Log Sector ECClogSector0~ECClogSector3 indicates the error position in the 2nd word and LSB of 3rd word in the spare area. Refer to note 2 in chapter 2.7.2 ECClogSector Information [5:4] ECClogSector 00 01 10, 11 FLASH MEMORY Error Position 2nd word 3rd word Reserved 83 ...
Page 84
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.0 DEVICE OPERATION This section of the datasheet discusses the operation of the MuxOneNAND device followed by AC/DC Characteristics and Timing Diagrams which may be consulted for further information. The MuxOneNAND supports a limited command-based interface in addition to a register-based interface for performing operations on the device. ...
Page 85
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.1.1 Reset MuxOneNAND Command The Reset command is given by writing 00F0h to the boot partition address. Reset will return all default values into the device. 3.1.2 Load Data Into Buffer Command Load Data into Buffer command is a two-cycle command. Two sequential designated command activates this operation. Sequentially writing 00E0h and 0000h to the boot partition [0000h~01FFh, 8000h~800Fh] will load one page to DataRAM0 ...
Page 86
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.2 Device Bus Operation The device bus operations are shown in the table below. Operation CE Standby H Warm Reset X Asynchronous Write L Asynchronous Read L Start Initial Burst Read L Burst Read L Terminate Burst Read H Cycle Terminate Burst Read X Cycle via RP Terminate Current Burst ...
Page 87
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.3 Reset Mode Operation The One NAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Flash Array Reset. Section 3.3 discusses the operation of these reset modes. The Register Reset Table shows the which registers are affected by the various types or Reset operations. ...
Page 88
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.3.1 Cold Reset Mode Operation See Timing Diagram 6.17 At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases an internal power-up reset signal. This triggers bootcode loading. Bootcode loading means that the boot loader in the device copies designated sized data (1KB) from the beginning of memory into the BootRAM ...
Page 89
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.4 Write Protection Operation The MuxOneNAND can be write-protected to prevent re-programming or erasure of data. The areas of write-protection are the BootRAM, and the NAND Flash Array. 3.4.1 BootRAM Write Protection Operation At system power-up, voltage detector in the device detects the rising edge of Vcc and releases the internal power-up reset signal which triggers bootcode loading ...
Page 90
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.4.3.1 Unlocked NAND Array Write Protection State An Unlocked block can be programmed or erased. The status of an unlocked block can be changed to locked or locked-tight using the appropriate software command. (locked-tight state can be achieved via lock-tight command which follows lock command) Only one block can be released from lock state to unlock state with Unlock command and addresses. The unlocked block can be changed with new lock command ...
Page 91
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.4.3.3 Locked-tight NAND Array Write Protection State A block that locked-tight state can only be changed to locked state after a Cold or Warm Reset. Unlock and Lock command sequences will not affect its state. This is an added level of write protection security. A block must first be set to a locked state before it can be changed to locked-tight using the Lock-tight command. locked-tight blocks will revert to a locked state following a Cold or Warm Reset ...
Page 92
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Data Protection Operation Flow Diagram Write ‘DFS*’, of Flash Add: F100h DQ=DFS* Select DataRAM for DDP Add: F101h DQ=DBS Write ‘SBA’ of Flash Add: F24Ch DQ=SBA Write 0 to interrupt register Add: F241h DQ=0000h Write ‘lock/unlock/lock-tight’ DQ=002Ah/0023h/002Ch Wait for INT register ...
Page 93
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) All Block Unlock Flow Diagram Note 1) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1 * Samsung strongly recommends to follow the above flow chart Start Write ’DFS*, of Flash Add: F100h DQ=DFS* Select DataRAM for DDP Add: F101h DQ=DBS Write ’ ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.5 Data Protection During Power Down Operation See Timing Diagram 6.21 The device is designed to offer protection from any involuntary program/erase during power-transitions. RP pin which provides hardware protection must be kept at VIL before Vcc drops to 1.5V. 3.6 Load Operation See Timing Diagrams 6.11 The Load operation is initiated by setting up the start address from which the data loaded. The Load command is issued in order to initiate the load ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.7 Read Operation See Timing Diagrams 6.1, 6.2, 6.5, and 6.6 The device has two read modes; Asynchronous Read and Synchronous Burst Read. The initial state machine automatically sets the device into the Asynchronous Read Mode (RM=0) to prevent the spurious altering of memory content upon device power up or after a Hardware reset. No commands are required to retrieve data in Asynchronous Read Mode ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.7.2.1 Continuous Linear Burst Read Operation See Timing Diagram 6.2 First Clock Cycle The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is ready to the system by pulsing high. If the device is accessed synchronously while it is set to Asynchronous Read Mode, the first data can still be read out ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.7.2.3 Programmable Burst Read Latency Operation See Timing Diagrams 6.1 and 6.2 Upon power up, the number of initial clock cycles from Valid Address (AVD) to initial data defaults to four clocks. The number of clock cycles (n) which are inserted after the clock which is latching the address. The host can read the first data with the (n+1)th rising edge ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.8 Cache Read Operation (RM=X, WM=X) A Normal Load Operation(0000h) consists of sequential operation of ’sensing from NAND Flash Array to Page Buffer’ and ’transfer- ring from Page Buffer to DataRAM’. Cache Read is a method of improving the data read throughput performance of the device by allowing new data to be transferred from the NAND Flash Array memory into a Page Buffer while the previous data that was requested is transferred from the Page Buffer to the DataRAM ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Cache Read Flow Chart Start Write ‘FCBA’ of Flash Add: F102h DQ=FCBA 2) Write ‘FCPA, FCSA ’ of Flash Add: F103h DQ=FCPA, FCSA 1) 2) Write ‘BSA , BSC ’ of Flash Add: F200h DQ=BSA, BSC Write ’DFS*, FBA’ of Flash Add: F100h DQ=DFS, FBA ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) ≈ ≈ ≈ ≈ 100 FLASH MEMORY ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.8.1 Interleaving Cache Read The Interleving Cache Read use for reading data which writed by 2X Interleaving Cache Program. Interleaving Cache Read flow chart Start Write ’FCBA’ of Flash Write ’DFS, FBA’ of Flash Add: F102h DQ=FCBA Add: F100h DQ=DFS, FBA Select DataRAM for DDP Write ’ ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.9 Synchronous Burst Block Read Operation See Timing Diagram 6.3 and 6.4. MuxOneNAND is internally composed of two DataRAMs and NAND Flash Array. And for host to read data from NAND Cell Array, load operation which moves data from NAND Cell Array to DataRAM is required. After this load operation, host may use various read mode, such as synchronous burst read or asynchronous read, to read data from MuxOneNAND ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.9.1 Burst Address Sequence During Synchronous Burst Block Read Mode In a Synchronous Burst Block Read, data is output with respect to a clock input. MuxOneNAND is capable of a continuous linear burst operation within one block size and a fixed-length linear burst operation of a preset length. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Synchronous Burst Block Read Boundary Read Sequence for Single Plane Device :note that only main area data is read. Page Page 63 Main Area FLASH MEMORY Not supported Spare Area 104 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.9.3 4-, 8-, 16-, 32-, 1K- Word Linear Burst Read Operation During Synchronous Burst Block Read Mode Same as normal linear burst read, synchronous burst block read enables a fixed number of words to be read from consecutive address. The device supports a burst read from consecutive addresses of 4-, 8-, 16-, 32- and 1K-words with no wrap. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.9.5 Handshaking Operation During Synchronous Burst Block Read Mode The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. To set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configuration (see Section 2.8.19, " ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.10 Synchronous Write(RM=1, WM=1) See Timing Diagram 6.8, 6.9 and 6.10. Burst mode operations enable high-speed synchronous read and write operations. Burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. After CE goes low, the address to access is latched on the next rising edge of clk that ADV is low ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.11 Program Operation See Timing Diagram 6.12 The Program operation is used to program data from the on-chip BufferRAMs into the NAND FLASH memory array. The device has two 2KB data buffers, each 1 Page (2KB + 64B) in size. Each page has 4 sectors of 512B each main area and 16B spare area ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Program Operation Flow Diagram Start 1) Select DataRAM for DDP Add: F101h DQ=DBS* 2) Write Data into DataRAM ADD: DP DQ=Data-in NO Data Input Completed? YES Write ’DFS*, FBA’ of Flash Add: F100h DQ=DFS*’, FBA Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write ’ ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.11.1 2X Program Operation See Timing Diagram 6.13 The 2X Program is an extension of Program Operation. Since the device is equipped with two DataRAMs, and two-plane NAND Flash memory array, these two component enables simultaneous program of 4KB. Plane1 has only even blocks such as block0, block2, block4 while Plane2 has only odd blocks such as block1, block3, block5. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2X Program Operation Flow Diagram Start 1) Select DataRAM for DDP Add: F101h DQ=DBS* 2) Write Data into DataRAM ADD: DP DQ=Data-in NO Data Input Completed? YES Write ’DFS*, FBA’ of Flash 3) Add: F100h DQ=DFS*’, FBA Write ’FPA, FSA’ of Flash 4) Add: F107h DQ=FPA, FSA 4) Write ’ ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.11.2 2X Cache Program Operation See Timing Diagram 6.14 The 2X Cache Program Operation is invented to accomplish continuous 2X Program Operation efficiently by hiding transferring time from DataRAM to page buffer.. 1. 4KB Data write from host to DataRAMs Cache Program command issue. This will turn INT pin to busy state (Note that before issuing ’ ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2X Cache Program Operation Flow Diagram Start 1) Select DataRAM for DDP Add: F101h DQ=DBS Write Data into DataRAM0,1 Add: DataRAM DQ=Data(4KB) Write ’DFS, FBA’ of Flash 2) Add: F100h DQ=DFS, FBA Write ’FPA, FSA’ of Flash 3) Add: F107h DQ=FPA, FSA 4) Write ’ ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.11.3 2X Interleave Cache Program Operation See Timing Diagram 6.15 The 2X Interleave Cache Program is available only on DDP. Host can write data on a chip while programming another chip with this operation. 2X Interleave Cache Program is executed as following: 1. 4KB Data are written from host to DataRAMs in Chip1. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 2X Interleave Cache Program Operation Flow Diagram Start 1) Select DataRAM for DDP Select DataRAM for DDP Add: F101h DQ=DBS Add: F101h DQ=DBS Write ’DFS, FBA’ of Flash Write Data into DataRAM0,1 Add: F100h DQ=DFS, FBA Add: DataRAM DQ=Data(4KB) Check INT register Write ’ ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.12 Copy-Back Program Operation The Copy-Back program is configured to quickly rewrite data stored in one page without utilizing memory other than OneNAND. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The ben- efit is especially obvious when a portion of block is updated and the rest of the block also need to be copied to the newly assigned free block ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) The Copy-Back steps shown in the flow chart are: • Data is read from the NAND Array using Flash Block Address (FBA), Flash Page Address (FPA) and Flash Sector Address (FSA). FBA, FPA, and FSA identify the source address to read data from NAND Flash array. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.12.1 Copy-Back Program Operation with Random Data Input The Copy-Back Program Operation with Random Data Input in MuxOneNAND consists of 2 phase, Load data into DataRAM, Modify data and program into designated page. Data from the source page is saved in one of the on-chip DataRAM buffers and modified by the host, then programmed into the destination page ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.13 Erase Operation There are multiple methods for erasing data in the device including Block Erase and Multi-Block Erase. 3.13.1 Block Erase Operation See Timing Diagram 6.16 The Block Erase Operation is done on a block basis. To erase a block is to write all 1's into the desired memory block by executing the Internal Erase Routine ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) In order to perform the Internal Erase Routine, the following command sequence is necessary. • The Host selects Flash Core of DDP chip. • The Host sets the block address of the memory location. • The Erase Command initiates the Internal Erase Routine. During the execution of the Routine, the host is not required to provide further controls or timings ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.13.3 Multi-Block Erase Verify Read Operation After a Multi-Block Erase Operation, verify Erase Operation result of each block with Multi-Block Erase Verify Command combined with address of each block failed address is identified, it must be managed by firmware. Multi Block Erase/ Multi Block Erase Verify Read Flow Chart ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.13.4 Erase Suspend / Erase Resume Operation The Erase Suspend/Erase Resume Commands interrupt and restart a Block Erase or Multi-Block Erase operation so that user may perform another urgent operation on the block that is not being designated by Erase/Multi-Block Erase Operation. Erase Suspend During a Block Erase Operation When Erase Suspend command is written during a Block Erase or Multi-Block Erase operation, the device requires a maximum of 500us to suspend erase operation ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Erase Resume When the Erase Resume command is executed, the Block Erase will restart. The Erase Resume operation does not actually resume the erase, but starts it again from the beginning. When an Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) OTP Block Area Structure Sector(main area):512B One Block: 64pages 128KB+4KB 1st Block OTP Area Structure Sector(main area):512B One Block: 64pages 128KB+4KB FLASH MEMORY Page:2KB+64B Manufacturer Area : Sector(spare area):16B 14pages page 50 to page 63 User Area : 50pages ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.14.1 OTP Block Load Operation An OTP Block Load Operation accesses the OTP area and transfers identified content from the OTP to the DataRAM on-chip buffer, thus making the OTP contents available to the Host. The OTP area is a separate part of the NAND Flash Array memory accessed by issuing OTP Access command(65h) instead of a Flash Block Address (FBA) command ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.14.2 OTP Block Program Operation An OTP Block Program Operation accesses the OTP area and programs content from the DataRAM on-chip buffer to the designated page(s) of the OTP. A memory location in the OTP area can be programmed only one time (no erase operation permitted). ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) OTP Block Program Operation Flow Chart Start 1) Write ’DFS*, FBA’ of Flash Add: F100h DQ=DFS*, FBA Select DataRAM for DDP Add: F101h DQ=DBS* 4) Write 0 to interrupt register Add: F241h DQ=0000h Write ’OTP Access’ Command Add: F220h DQ=0065h ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.14.3 OTP Block Lock Operation Even though the OTP area can only be programmed once without erase capability, it can be locked when the device starts up to pre- vent any changes from being made. Unlike the main area of the NAND Flash Array memory, once the OTP block is locked, it cannot be unlocked, for locking bit for both blocks lies in the same word of OTP area ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) OTP Block Lock Operation Flow Chart Start Write ’DFS’, ’FBA’ of Flash Add: F100h DQ=DFS, FBA Select DataRAM for DDP Add: F101h DQ=DBS* Write 0 to interrupt register Add: F241h DQ=0000h Write ’OTP Access’ Command Add: F220h DQ=0065h ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.14.4 1st Block OTP Lock Operation 1st Block could be used as OTP, for secured booting operation. 1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP, 1st Block OTP cannot be erased or programmed. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 1st Block OTP Lock Operation Flow Chart Start Write ’DFS’, ’FBA’ of Flash Add: F100h DQ=DFS, FBA Select DataRAM for DDP Add: F101h DQ=DBS* Write 0 to interrupt register Add: F241h DQ=0000h Write ’OTP Access’ Command Add: F220h DQ=0065h ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.14.5 OTP and 1st Block OTP Lock Operation OTP and 1st Block can be locked simultaneously, for locking bit lies in the same word of OTP area. 1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP, 1st Block OTP cannot be erased or programmed ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) OTP and 1st Block OTP Lock Operation Flow Chart Start Write ’DFS’, ’FBA’ of Flash Add: F100h DQ=DFS, FBA Select DataRAM for DDP Add: F101h DQ=DBS* Write 0 to interrupt register Add: F241h DQ=0000h Write ’OTP Access’ Command ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.15 Dual Operations The device has independent dual data buffers on-chip (except during the Boot Load period) that enables higher performance read and program operation. 3.15.1 Read-While-Load Operation This operation accelerates the read performance of the device by enabling data to be read out by the host from one DataRAM buffer while the other DataRAM buffer is being loaded with data from the NAND Flash Array memory ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) FLASH MEMORY 135 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) FLASH MEMORY 136 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.16 DQ6 Toggle Bit The MuxOneNAND device has DQ6 Toggle bit. Toggle bit is another option to detect whether an internal load operation is in progress or completed. Once the BufferRAM(BootRAM, DataRAM0, DataRAM1 busy state during internal load operation, DQ6 will tog- gle. Toggling DQ6 will stop after the device completes its internal load operation. The MuxOneNAND device’s DQ6 Toggle will be valid only when host reads BufferRAM designated by BSA which will be loaded by internal load operation ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.17 ECC Operation The MuxOneNAND device has on-chip ECC with the capability of detecting 2 bit errors and correcting 1-bit errors in the NAND Flash Array memory main and spare areas. As the device transfers data from a BufferRAM to the NAND Flash Array memory Page Buffer for Program Operation, the device ini- tiates a background operation which generates an Error Correction Code (ECC) of 24bits for each sector main area data and 10bits for 2nd and 3rd word data of each sector spare area ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 3.18 Invalid Block Operation Invalid blocks are defined as blocks in the device's NAND Flash Array memory that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is called the Invalid Block Information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
Page 140
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Invalid Block Table Creation Flow Chart Increment Block Address Create (or update) Invalid Block(s) Table 3.18.2 Invalid Block Replacement Operation Within its life time, additional invalid blocks may develop with NAND Flash Array memory. Refer to the device's qualification report for the actual data ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Referring to the diagram for further illustration, when an error happens in the nth page of block 'A' during program operation, copy the data in the 1st ~ (n-1)th page to the same location of block 'B' via data buffer0. Then copy the nth page data of block 'A' in the data buffer1 to the nth page of block 'B' or any free block. Do not further erase or program block 'A' but instead complete the operation by creating an 'Invalid Block Table' or other appropriate scheme ...
Page 142
... Vcc-Core (or Vcc) should reach the operating voltage level prior the same time as Vcc-IO (or Vccq). Symbol Vcc Vcc All Pins V IN Extended T bias Industrial T stg (Extended Temp (Industrial Temp.) A KFM2G16Q2M Symbol Min core / Vcc 1 Vccq 142 FLASH MEMORY Rating Unit -0 2. 2.45 -30 to +125 °C -40 to +125 °C -65 to +150 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 4.3 DC Characteristics Parameter Symbol Input Leakage Current I Output Leakage Current I LO Active Asynchronous Read Current I CC1 (Note 2) Active Burst Read Current (Note 2) I CC2R Active Burst Write Current (Note 2) I CC2W Active Asynchronous Write Current I CC3 (Note 2) Active Load Current (Note 3) ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 5.0 AC CHARACTERISTICS 5.1 AC Test Conditions Parameter Input Pulse Levels CLK Input Rise and Fall Times other inputs Input and Output Timing Levels Output Load V CC Input & Output Test Point 0V Input Pulse and Test Point 5.2 Device Capacitance CAPACITANCE = 25 ° ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 5.4 AC Characteristics for Synchronous Burst Read See Timing Diagrams 6.1, 6.2, 6.3, 6.4 and 6.24 Parameter Clock Clock Cycle Initial Access Time Burst Access Time Valid Clock to Output Delay AVD Setup Time to CLK AVD Hold Time from CLK AVD High to OE Low Address Setup Time to CLK ...
Page 146
... RP Pulse Width (Note2) Note: 1. These parameters are tested based on INT bit of interrupt register. Because the time on INT pin is related to the pull-up and pull-down resistor value. 2. The device may reset if tRP < tRP min(200ns), but this is not guaranteed. FLASH MEMORY KFM2G16Q2M/ KFN4G16Q2M/ Symbol KFK8G16Q2M Min ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 5.7 AC Characteristics for Asynchronous Write See Timing Diagrams 6.7 Parameter WE Cycle Time AVD low pulse width Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE Setup Time CE Hold Time WE Pulse Width WE Pulse Width High WE Disable to AVD Enable CE Low to RDY Valid CE Disable to Output & ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 5.9 AC Characteristics for Load/Program/Erase Performance See Timing Diagrams 6.11, 6.12, and 6.16 Parameter Sector Load time(Note 1) Page Load time(Note 1) Sector Program time(Note 1) Page Program time(Note 1) OTP Access Time(Note 1) Lock/Unlock/Lock-tight/All Block Unlock Time(Note 1) Erase Suspend Time(Note 1) Erase Resume Time(Note 1) Number of Partial Program Cycles in the page (Including main and ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.0 TIMING DIAGRAMS 6.1 8-Word Linear Burst Read Mode with Wrap Around See AC Characteristics Table 5.4 BRWL = CLK CES CER CER - CLK t RDYO t AVDS t AVD AVDO t AVDH t ACS A/DQ0: A/DQ15 t ACH t OE Hi-Z RDY 6.2 Continuous Linear Burst Read Mode with Wrap Around See AC Characteristics Table 5 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) FLASH MEMORY 150 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) FLASH MEMORY 151 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) ≈ ≈ ≈ ≈ ≈ ≈ ≈ 152 FLASH MEMORY ≈ ≈ ...
Page 153
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.5 Asynchronous Read See AC Characteristics Table 5 OEH WE A/DQ0: A/DQ15 t AAVDS t AVD WEA Hi-Z RDY NOTE: VA=Valid Read Address, RD=Read Data. See timing diagram 6.22, 6.23 for tASO 6.6 Asynchronous Read See AC Characteristics Table 5 CER OE t OEH WE A/DQ0: A/DQ15 t WEA AVD Hi-Z RDY NOTE: VA=Valid Read Address, RD=Read Data ...
Page 154
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.7 Asynchronous Write See AC Characteristics Table 5 CLK AAVDS AVD t AVDP ADQ15-ADQ0 Hi-Z RDY t CER WPL WPH t WEA t AAVDH VA Valid WD VA NOTE: VA=Valid Read Address, WD=Write Data. 154 FLASH MEMORY t t CEZ CH Valid ...
Page 155
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.8 8-Word Linear Burst Write Mode See AC Characteristics Table 5.8 BRWL = CLK CES CER CER - CLK t RDYO t AVDS AVD t AVDH t ACS A/DQ0: A/DQ15 t ACH OE t WES WE t WEH Hi-Z RDY 6.9 Burst Write Operation followed by Burst Read See AC Characteristics Table 5.8 ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.10 Start Initial Burst Write Operation See AC Characteristics Table 5.8 BRWL = CES CLK CER CER - CLK t RDYO t AVDS AVD t AVDH t ACS A/DQ0: A/DQ15 t ACH OE t WES WE t WEH Hi-Z RDY t CEHP t t CLKH CLKL t CEH t CEZ ...
Page 157
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.11 Load Operation Timing See AC Characteristics Tables 5.5, 5.7 and 5.9. Load Command Sequence (last two cycles) t AAVDS AVD t AVDP t AAVDH AA LMA ADQ0~ CER OE t WPL CLK INT bit Hi-Z RDY NOTES Address of address register CA = Address of command register LCD = Load Command ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.12 Program Operation Timing See AC Characteristics Tables 5.5, 5.7 and 5.9. Program Command Sequence (last two cycles AVDP WEA AVD t AAVDS t AAVDH A/DQ0: AA PMA BA A/DQ15 WPL WE t WPH CLK t CER INT bit Hi-Z RDY NOTES Address of address register ...
Page 159
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.13 2X Program Operation Timing Address Setting . . . . ADQ0~ A1 1st data input ADQ15 4KB data into 2 DataRAMs Ongoing Status INT 2X program Command A1 : Address of DataRAM to be written. INT: Indicator for DataRAM’s Status (Ready=High, Busy=Low) Ongoing Status : Indicated by OnGo bit in Controller Status Register [15] (F240h) 4KB data input : Asynch Write / Synch Write available. Command input and INT pin behavior is based on ’ ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) FLASH MEMORY 160 ...
Page 161
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) FLASH MEMORY 161 ...
Page 162
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.16 Block Erase Operation Timing See AC Characteristics Tables 5.5, 5.7 and 5.9. Erase Command Sequence t AAVDS t WEA AVD t AVDP t AAVDH A/DQ0: AA EMA A/DQ15 WPL t CER WE t WPH CLK INT bit Hi-Z RDY NOTES Address of address register CA = Address of command register ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.17 Cold Reset Timing POR triggering level System Power MuxOneNAND Sleep Operation RP INT INT bit IOBE bit INTpol bit Note: 1) Bootcode copy operation starts 400us later than POR activation. The system power should reach Vcc after POR triggering level(typ. 1.5V) within 400us for valid boot code data. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.18 Warm Reset Timing See AC Characteristics Tables 5.6. CE Ready1 High-Z RDY INT bit Operation 1) Idle Reset Ongoing Status NOTES: 1. The status which can accept any register based operation(Load, Program, Erase command, etc). 2. The status where reset is ongoing. ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.19 Hot Reset Timing See AC Characteristics Tables 5.6. AVD BP(Note 3) ADQi or F220h INT bit High-Z RDY MuxOneNAND Operation or Idle Operation NOTE: 1. Internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferRAM data are kept unchanged after Warm/Hot reset operations ...
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... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.20 NAND Flash Core Reset Timing AVD ADQi F220h INT bit High-Z RDY MuxOneNAND Operation or Idle Operation 6.21 Data Protection Timing During Power Down The device is designed to offer protection from any involuntary program/erase during power-transitions. RP pin provides hardware protection and must be kept at V before Vcc drops to 1 ...
Page 167
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.22 Toggle Bit Timing in Asynchronous Read (VA Transition Before AVD Low) See AC Characteristics Table 5 CER ASO t AVDO A/DQ0 A/DQ15 t AAVDS t AAVDH AVD t AVDP RDY NOTE: 1. VA=Valid Read Address, RD=Read Data. 2. Before IOBE is set to 1, RDY and INT pin are High-Z state. ...
Page 168
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 6.24 Toggle Bit Timing in Synchronous Read Mode See AC Characteristics Tables 5.4. t CES CE CLK t AVDS AVD t AVDH t ACS A/DQ0 A/DQ15 t ACH t IAA OE Hi-Z 2) RDY NOTE : Valid Address. When the Internal Routine operation is complete, the toggle bits will stop toggling. ...
Page 169
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 7.0 TECHNICAL AND APPLICATION NOTES From time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a system are included in this section. Contact your Samsung Representative to determine if additional notes are available. 7.1 Methods of Determining Interrupt Status There are two methods of determining Interrupt Status on the MuxOneNAND ...
Page 170
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 7.1.1 The INT Pin to a Host General Purpose I/O INT can be tied to a Host GPIO to detect the rising edge of INT, signaling the end of a command operation. COMMAND INT This can be configured to operate either synchronously or asynchronously as shown in the diagrams below. Synchronous Mode Using the INT Pin When operating synchronously, INT is tied directly to a Host GPIO ...
Page 171
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 7.1.2 Polling the Interrupt Register Status Bit An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of using the INT pin. When using interrupt register instead of INT pin, INT pin is recommended to float to avoid power consumption at IOBE=0(disable). ...
Page 172
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 7.1.3 Determining Rp Value (DDP, QDP Only) For general operation, INT operates as normal output pin, so that tF is equivalent to tR (below 10ns). But since INT operates as open drain with 50K ohm for Reset (Cold/Hot/Warm/NAND Flash Core) operations and ’2X program operation’ case at DDP option, the pull-up resistor value is related to tr(INT) ...
Page 173
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Vcc or Vccq INT ~50k ohm KFN4G16Q2M @ Vcc = 1.8V 25° 1.76 Ibusy 0.111 tf[us] 7.53 tr[ns] 1K INT pol = ’Low’ tr Ready Rp VOH Vss = 30pF L 3.012 2.655 0.18 2.218 0.09 0.06 0.959 1.669 0.045 0.036 6.73 6.71 6.74 6.81 6.92 30K 10K 20K 50K 40K Rp(ohm) 173 FLASH MEMORY tf Vcc Busy State VOL 4 ...
Page 174
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 7.2 Boot Sequence One of the best features MuxOneNAND has is that it can be a booting device itself since it contains an internally built-in boot loader despite the fact that its core architecture is based on NAND Flash. Thus, MuxOneNAND does not make any additional booting device necessary for a system, which imposes extra cost or area overhead on the overall system ...
Page 175
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) Block 2047 Reservoir Reservoir File System File System Block 162 Block 162 Os Image Os Image Block 2 Block 2 NBL3 BL3 Block 1 Block 1 NBL1 BL1 NBL2 BL2 Block 0 Block 0 Reservoir File System Os Image BL1 BL2 step 1 NAND Flash Array MuxOneNAND NOTE: ...
Page 176
... MAX 0.80x9=7.20 (Datum (Datum 3.60 0.32 ±0.05 0.9 ±0.10 BOTTOM VIEW 63- ∅ 0.45 ±0.05 ∅ 0. product (KFM2G16Q2M) 0.10 MAX 0.80x9=7.20 (Datum (Datum 3.60 0.32 ±0.05 1.1 ±0.10 BOTTOM VIEW 63- ∅ 0.45 ±0.05 ∅ 0. ...
Page 177
... MuxOneNAND2G(KFM2G16Q2M-DEBx) MuxOneNAND4G(KFN4G16Q2M-DEBx) MuxOneNAND8G(KFK8G16Q2M-DEBx) 10.00 ±0.10 #A1 TOP VIEW 0.10 MAX 0.80x9=7.20 (Datum (Datum 3.60 0.32 ±0.05 1.3 ±0.10 BOTTOM VIEW 63- ∅ 0.45 ±0.05 ∅ 0. product (KFK8G16Q2M) 177 FLASH MEMORY #A1 INDEX 10.00 ±0. ...