kfm2g16q2m-deb8 Samsung Semiconductor, Inc., kfm2g16q2m-deb8 Datasheet - Page 2

• Manufacturer Part Number: kfm2g16q2m-deb8
• Description: 2gb Muxonenand M-die
• Manufacturer: Samsung Semiconductor, Inc.

Revision History
Document Title
MuxOneNAND
Revision History
Revision No.
MuxOneNAND2G(KFM2G16Q2M-DEBx)
MuxOneNAND4G(KFN4G16Q2M-DEBx)
MuxOneNAND8G(KFK8G16Q2M-DEBx)
0.0
0.1
1.0
1.1
History
1. Initial issue.
1. Corrected errata.
2. Changed a tem from MAT to Plane.
3. Chapter 1.4 & 2.3 & 8.0 : Revised the package size from 11x13 to 10x13.
4. Chapter 2.8.3 : Eliminated ’Top boot’ option.
5. Chapter 2.8.12 & 2.8.16 & 3.8 : Added a. comment about FSA & FCSA
6. Chapter 2.8.18 : Added acceptible command during busy on Unlock,
7. Chapter 3.1 : Eliminated ’read data from buffer’ and ’write data to buffer’
8. Chapter 3.3 : Revised default value on Start Block Address with hot reset.
9. Chapter 3.3.1& 4.2 & 6.17 : Revised the bootcode copy condtions.
10. Chapter 3.5 : Revised POR level into 1.5V and resetting guidance.
11. Chapter 3.11.1~3 : Added details and restrictions about 2X program and
12. Chapter 3.11.3 & 6.16 : Revised mandatory codition which is ’INT auto
13. Chapter 3.13.2 : Eliminated the expression ’suspended’ on Case 2.
14. Chapter 3.14.1 : Revised Note 1 on OTP load flow chart.
15. Chapter 4.3 : Revised
16. Chapter 4.3 : Revised Load/Program/Erase current value and added
17. Chapter 5.4 : Revised tBDH(into 2ns on 83Mhz) and tAVDH(into 2ns on
18. Chapter 5.8 : Revised tAVDH(into 2ns on 66/83Mhz)
19. Chapter 5.10 : Revised tWB table.
20. Chapter 5.11 : Revised tINTL table and its value.
21. Chapter 6.16 : Revised Block erase operation timing.
22. Chapter 6.21 : Revised timing diagram.
1. Corrected errata.
2. Chapter 3.1 : Added restrictions of command based operation on DDP.
3. Chapter 3.5 & 6.21 : Corrected data protection explanation during power-
4. Chapter 7.1 & 7.1.2 : Added the case table of INT type and comment
5. Chapter 7.1.3 : Corrected INT behavior graphs.
1. Chapter 2.8.19 Burst Length revised.
2. Chapter 2.8.21 Controller Status Register Output Modes revised.
3. Chapter 2.8.23 SBA description table updated.
4. Chapter 2.8.26 ECC Status Register revised.
5. Chapter 3.1 Reading Data FromBuffer writing Data to Buffer erased.
6. Chapter 3.3 Reset mode revised.
7. Chapter 3.7.1 WM revised.
8. Chapter 3.8 Cache read flow chart updated.
9. Chapter 3.8.1 Interleaving Cache Read updated.
10. Chapter 3.9.1 table erased.
down.
regarding INT pin connection when unused.
setting on Cache Read Operation
Lock, Lock-tight, All block unlock and Erase suspend operation.
contents.
2X Cache Program.
mode for 2X interleave Cache Program’ into manually writable INT cond-
tion as 2X Program or 2X Cache Program.
"2X Program current" item.
66/83Mhz).
2
Draft Date
Apr. 3, 2006
Aug., 3, 2006
Sep. 20, 2006
May, 30, 2007
FLASH MEMORY
Remark
Advanced
Preliminary
Final
Final