kfm2g16q2m-deb8 Samsung Semiconductor, Inc., kfm2g16q2m-deb8 Datasheet - Page 87

• Manufacturer Part Number: kfm2g16q2m-deb8
• Description: 2gb Muxonenand M-die
• Manufacturer: Samsung Semiconductor, Inc.

3.3
Internal Register Reset Table
NOTE: 1a) RDYpol, RDY conf, INTpol, IOBE are reset by Cold reset. The other bits are reset by cold/warm/hot reset.
MuxOneNAND2G(KFM2G16Q2M-DEBx)
MuxOneNAND4G(KFN4G16Q2M-DEBx)
MuxOneNAND8G(KFK8G16Q2M-DEBx)
The One NAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Flash Array Reset. Section 3.3 discusses the operation of
these reset modes.
The Register Reset Table shows the which registers are affected by the various types or Reset operations.
F24Ch
F24Dh
F24Eh
F000h
F001h
F002h
F003h
F004h
F005h
F006h
F100h
F101h
F102h
F103h
F104h
F107h
F200h
F220h
F221h
F240h
F241h
FF00h
FF01h
FF02h
FF03h
FF04h
FF05h
FF06h
FF07h
FF08h
1b) The other bits except OTP
2) ECC Status Register & ECC Result Registers are reset when any command is issued.
3) Refer to Device ID Register F001h.
4) Refer to Version ID Register F002h.
5) Resetting during IDLE state, this is valid. But resetting during BUSY state, refer to Chapter 2.8.21.
Manufacturer ID Register (R)
Device ID Register (R): MuxOneNAND
Version ID Register (R)
Data Buffer size Register (R)
Boot Buffer size Register (R)
Amount of Buffers Register (R)
Technology Register (R)
Start Address1 Register (R/W): DFS, FBA
Start Address2 Register (R/W): DBS
Start Address3 Register (R/W): FCBA
Start Address4 Register (R/W): FCPA, FCSA
Start Address5 Register (R/W): FPC
Start Address8 Register (R/W): FPA, FSA
Start Buffer Register (R/W): BSA, BSC
Command Register (R/W)
System Configuration 1 Register (R/W)
Controller Status Register (R)
Interrupt Status Register (R/W)
Start Block Address (R/W) :SBA
End Block Address: N/A
NAND Flash Write Protection Status (R)
ECC Status Register (R) (Note2)
ECC Result of Sector 0 Main area data Register(R)
ECC Result of Sector 0 Spare area data Register (R)
ECC Result of Sector 1 Main area data Register(R)
ECC Result of Sector 1 Spare area data Register (R)
ECC Result of Sector 2 Main area data Register(R)
ECC Result of Sector 2 Spare area data Register (R)
ECC Result of Sector 3 Main area data Register(R)
ECC Result of Sector 3 Spare area data Register (R)
Reset Mode Operation
Internal Registers
L
and OTP
BL
(Note1b) (Note5)
are reset by cold/warm/hot reset.
(Note 3)
(Note 4)
Default Cold Reset
00ECh
40C0h
0800h
0200h
0201h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N/A
-
87
40C0h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
8080h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Warm Reset
(Note1a)
0000h
0000h
0000h
0000h
0000h
0000h
0002h
0000h
0000h
0000h
0000h
8010h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(RP)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(00F3h)
FLASH MEMORY
Reset
Hot
(Note1a)
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
8010h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
(BP-F0h)
Reset
Hot
NAND Flash
Core Reset
(00F0h)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A