kfm2g16q2m-deb8 Samsung Semiconductor, Inc., kfm2g16q2m-deb8 Datasheet - Page 107

• Manufacturer Part Number: kfm2g16q2m-deb8
• Description: 2gb Muxonenand M-die
• Manufacturer: Samsung Semiconductor, Inc.

MuxOneNAND2G(KFM2G16Q2M-DEBx)
MuxOneNAND4G(KFN4G16Q2M-DEBx)
FLASH MEMORY
MuxOneNAND8G(KFK8G16Q2M-DEBx)
3.10
Synchronous Write(RM=1, WM=1)
See Timing Diagram 6.8, 6.9 and 6.10.
Burst mode operations enable high-speed synchronous read and write operations. Burst operations consist of a multi-clock sequence
that must be performed in an ordered fashion. After CE goes low, the address to access is latched on the next rising edge of clk that
ADV is low. During this first clock rising edge, WE indicates whether the operation is going to be a read (WE = high) or write (WE =
low). The size of a burst can be specified in the BL as either a fixed length or continuous. Fixed-length bursts consist of 4, 8, 16, and
32 words. Continuous burst write has the ability to start at a specified address and burst within the designated DataRAM. The latency
count stored in the BRWL defines the number of clock cycles that elapse before the initial data value is transferred between the pro-
cessor and MuxOneNAND device.
The RDY output will be asserted as soon as a burst is initiated, and will be de-asserted to indicate when data is to be transferred into
(or out of) the memory. The processor can access other devices without incurring the timing penalty of the initial latency for a new
burst by suspending burst mode. Bursts are suspended by stopping clk. clk can be stopped high or low.
To continue the burst sequence, clk is restarted after valid data is available on the bus.
Same as the normal burst mode, the latency is determined by the host based on the BRWL bit setting in the System Configuration 1
Register. The default BRWL is 4 latency cycles. At clock frequencies of 40MHz or lower, latency cycles can be reduced to 3, at fre-
quency range from 40MHz to 66MHz, latency cycle should be over 4. And at 83MHz frequency, BRWL should be set to 6. BRWL can
be set up to 7 latency cycles.
For BufferRAMs, both ’Start Initial Burst Write’ and ’Burst Write’ is supported. (Refer to Chapter 3.2)
However, for Register Access, only ’Start Initial Burst Write’ is supported. Therefore, Synchronous Burst Write on Register is prohib-
ited. (Refer to Chapter 3.2 and 6.10)
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