h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 13

• Manufacturer Part Number: h5tq4g43mmr
• Description: 4gb Ddr3 Sdram Ddp
• Manufacturer: Hynix Semiconductor

Rev. 0.1 /Aug 2008
2.2 CKE Truth Table
a) Notes 1-7 apply to the entire CKE Truth Table.
b) CKE low is allowed only if tMRD and tMOD are satisfied.
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during
6. tCKEmin of [TBD] clocks means CKE must be registered on [TBD] consecutive positive clock edges. CKE must remain
7. DESELECT and NOP are defined in the Command Truth Table.
8. On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS
9. Self-Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
12. Valid commands for Self-Refresh Exit are NOP and DESELECT only.
13. Self-Refresh can not be entered during Read or Write operations. For a detailed list of restrictions
14. The Power-Down does not perform any refresh operations.
15. “X” means “don’t care” (including floating around VREF) in Self-Refresh and Power-Down. It also applies to
16. VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down
18. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high,
Current State
Bank(s) Active
All Banks Idle
Power-Down
Self-Refresh
Precharging
not included here.
Self-Refresh.
at the valid input level the entire time it takes to achieve the [TBD] clocks of registration. Thus, after any CKE
transition, CKE may not transition from its valid level during the time period of tIS + [TBD] + tIH.
period. Read or ODT commands may be issued only after tXSDLL is satisfied.
Refreshing
Address pins.
is entered, otherwise Active Power-Down is entered.
all Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as
see 8.1 on page 36.
Reading
Writing
For more details with all signals See “2.1 Command Truth Table” on page 11..
2
Previous
Cycle
(N-1)
H
H
H
H
H
H
H
L
L
L
L
1
CKE
Current
Cycle
(N)
H
H
L
L
L
L
L
L
L
L
L
1
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
Command (N)
RAS, CAS,
REFRESH
WE, CS
X
X
3
Precharge Power-Down Entry
Precharge Power-Down Entry
Active Power-Down Entry
Maintain Power-Down
Maintain Self-Refresh
Power-Down Entry
Power-Down Entry
Power-Down Entry
Power-Down Exit
Self-Refresh Exit
Action (N)
Self-Refresh
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
3
11,13,14,17
11,13,14,17
11,13,14,17
11,13,14,18
11,13,14
8,12,16
9,13,18
Notes
14, 15
15,16
11,14
10
11
13