h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 54

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h5tq4g43mmr

Manufacturer Part Number
h5tq4g43mmr
Description
4gb Ddr3 Sdram Ddp
Manufacturer
Hynix Semiconductor
Datasheet
Rev. 0.1 /Aug 2008
Timing Parameters by Speed Bin (Continued)
Note: The following general notes from page 58 apply to Table : a
ACT to internal read or write
delay time
Mode Register Set command
cycle time
Mode Register Set command
update delay
PRE command period
ACT to ACT or REF
command period
CAS to CAS command delay
Auto precharge write
recovery + precharge time
End of MPR Read burst to
MSR for MPR (exit)
ACTIVE to PRECHARGE
command period
ACTIVE to ACTIVE
command period for 1KB
page size
ACTIVE to ACTIVE
command period for 2KB
page size
Four activate window for 1KB
page size
Four activate window for 2KB
page size
Command and Address
setup time to CK, CK
referenced to Vih (ac) / Vil
(ac) levels
Command and Address hold
time from CK, CK referenced
to Vih (dc) / Vil (dc) levels
Command and Address
setup time to CK, CK
referenced to Vih (ac) / Vil
(ac) levels
Calibration Timing
Power-up and RESET
calibration time
Normal operation Full
calibration time
Normal operation Short
calibration time
Reset Timing
Parameter
tDAL (min)
tIS (base)
tIH (base)
tIS (base)
Symbol
tZQoper
tMPRR
AC150
tZQCS
tZQinit
tMRD
tMOD
tRCD
tCCD
tRRD
tRRD
tFAW
tFAW
tRAS
tRC
tRP
(4nCK, 10ns)
(12nCK
, 7.5ns)
, 15ns)
(4nCK
max
max
max
37.5
Min
125
200
512
256
50
64
4
4
1
DDR3-1066
-
Max
-
-
-
-
-
-
-
-
-
-
-
-
(4nCK, 6ns)
(12nCK
65+125
, 15ns)
(4nCK,
7.5ns)
max
max
max
Min
140
512
256
30
45
65
64
4
4
1
DDR3-1333
Max
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
-
-
-
-
-
-
-
-
-
-
-
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ps
ps
ps
Notes
b, 16,
b, 16
b, 16
22
27
23
e
e
e
e
e
e
e
e
54

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