h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 9

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h5tq4g43mmr

Manufacturer Part Number
h5tq4g43mmr
Description
4gb Ddr3 Sdram Ddp
Manufacturer
Hynix Semiconductor
Datasheet
Rev. 0.1 /Aug 2008
Note:
Input only pins (BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.
DQSU, DQSU,
TDQS, TDQS
DQSL, DQSL
DQU, DQL,
DQS, DQS,
Symbol
V
V
V
V
REFDQ
REFCA
V
V
DQ
NC
ZQ
DDQ
SSQ
DD
SS
Input /
Output
Input /
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Type
Data Input/ Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data,
centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU
corresponds to the data on DQU0-DQU7. The data strobe DQS, DQSL, and DQSU are paired
with differential signals DQS, DQSL, and DQSU, respectively, to provide differential pair
signaling to the system during reads and writes. DDR3 SDRAM supports differential data
strobe only and does not support single-ended.
Termination Data Strobe: TDQS/TDQS is applicable for x8 DRAMs only. When enabled via
Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance
function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11 =
0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. x4 DRAMs
must disable the TDQS function via mode register A11 = 0 in MR1.
No Connect: No internal electrical connection is present.
DQ Power Supply: 1.5 V +/- 0.075 V
DQ Ground
Power Supply: 1.5 V +/- 0.075 V
Ground
Reference voltage for DQ
Reference voltage
Reference Pin for ZQ calibration
Function
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
9

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