h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 51

• Manufacturer Part Number: h5tq4g43mmr
• Description: 4gb Ddr3 Sdram Ddp
• Manufacturer: Hynix Semiconductor

Rev. 0.1 /Aug 2008
Speed Bin Table Notes
Absolute Specification (T
Notes:
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all
3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK (AVG) down to the
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not
9. It is not a mandatory bin. Refer to supplier’s data sheet and/or the DIMM SPD information.
10. If it’s supported, the minimum tAA/tRCD/tRP that this device support is 13.125ns. Therefore, In Module application,
tAA/tRCD/tRP should be programed with minimum supported values. For example, DDR3-1333H supporting down-shift to
DDR3-1066F should program SPD as 13.125ns for tAAmin(Byte16)/tRCDmin(Byte18)/tRP(Byte20). DDR3-1600K support-
ing down-shift to DDR3-1333H and/or DDR3-1066F should program SPD as 13.125ns for tAAmin(Byte16)/tRCD-
min(Byte18)/tRP(Byte20).
11. Electrical Characteristics and AC Timing
Timing Parameters by Speed Bin
Note: The following general notes from page 58 apply to Table : a
Clock Timing
Minimum Clock Cycle Time
(DLL off mode)
Average Clock Period
Average high pulse width
Average low pulse width
Absolute Clock Period
tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK (AVG) [ns], rounding up to the
tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard
next ‘Supported CL’.
next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CLSE
LECTED.
Refer to supplier’s data sheet and SPD information if and how this setting is supported.
subject to Production Tests but verified by Design/Characterization.
subject to Production Tests but verified by Design/Characterization.
subject to Production Tests but verified by Design/Characterization.
Parameter
OPER
; V
DDQ
(DLL_OFF)
tCK (avg)
tCH (avg)
tCL (avg)
Symbol
(abs)
= V
tCK
tCK
DD
= 1.5V +/- 0.075 V);
min + tJIT
(avg)
(per)
0.47
0.47
Min
tCK
min
8
DDR3-1066
max +
(avg)
(per)
Max
0.53
0.53
max
tCK
tJIT
-
min + tJIT
(avg)
(per)
0.47
0.47
Min
tCK
min
8
DDR3-1333
max +
(avg)
(per)
Max
0.53
0.53
max
tCK
tJIT
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
-
Units
(avg)
(avg)
tCK
tCK
ns
ps
ps
Notes
6
f
f
f
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