h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 65

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h5tq4g43mmr

Manufacturer Part Number
h5tq4g43mmr
Description
4gb Ddr3 Sdram Ddp
Manufacturer
Hynix Semiconductor
Datasheet
Rev. 0.1 /Aug 2008
Figure 5 - Illustration of tangent line for setup time t
(for ADD/CMD with respect to clock).
Note: Clock and Strobe are drawn
on a different time scale.
V
V
V
V
V
V
IL(dc)
IL(ac)
IH(ac)
IH(dc)
DDQ
REF(dc)
DQS
DQS
CK
CK
max
max
min
min
V
nominal
SS
line
V
region
REF
to ac
TF
tDS
Setup Slew Rate
tVAC
Setup Slew Rate
tIS
tangent
Falling Signal
Rising Signal
line
tDH
tIH
DS
(for DQ with respect to strobe) and t
nominal
=
line
=
tangent line [V
tangent line [V
TR
tIS
tVAC
tDS
tangent
line
IH(ac)
∆TR
REF(dc)
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
∆TF
tIH
tDH
V
REF
min - V
region
- V
to ac
IS
IL(ac)
REF(dc)
max]
65
]

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