h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 218
h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 218 of 570
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7.4.8
The priority of the DMAC channels is: channel 0 > channel 1 > channel 2> channel 3. Table 7.3
shows the DMAC channel priority.
Table 7.3
If transfer requests occur simultaneously for a number of channels, the highest-priority channel
according to the priority in table 7.3 is selected for transfer.
Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode): If
transfer requests for different channels are issued during a transfer operation, the highest-priority
channel (excluding the currently transferring channel) is selected. The selected channel begins
transfer after the currently transferring channel releases the bus. If there is a bus request from a bus
master other than the DMAC at this time, a cycle for the other bus master is initiated. If there is no
other bus request, the bus is released for one cycle.
Channels are not switched during burst transfer or transfer of a block in block transfer mode.
Figure 7.13 shows an example of the transfer timing when transfer requests occur simultaneously
for channels 0, 1, and 2. The example in the figure is for external request cycle steal mode.
Rev. 2.00, 03/04, page 186 of 534
Channel
Channel 0
Channel 1
Channel 2
Channel 3
Channel Priority
DMAC Channel Priority
Priority
High
Low
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