h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 364

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

12.3.11 EP3 Data Register (EPDR3)
EPDR3 is a 64-byte transmit FIFO buffer for endpoint 3. EPDR3 stores one packet of transmit
data in the interrupt transfer for endpoint 3. If one packet of data is written and number of transmit
data is written in the packet enable register 3 (PKTE3), transmit data is valid. If one packet of data
is transmitted normally and the ACK handshake is returned from the host, the EP3TS bit in IFR0
is set. EPDR3 can be initialized by setting the EP3CLR bit in the FIFO clear register 0.
12.3.12 Data Status Register 0 (DASTS0)
DASTS0 indicates whether the IN FIFO data registers contain valid data or not. A bit in DASTS0
is set to 1 when data written to the corresponding IN FIFO becomes valid after the number of
transfer bytes is written in the packet enable register. A bit in DASTS0 is cleared to 0 when all
valid data is sent to the host. For endpoint 2, having a dual-FIFO configuration, the corresponding
bit in DASTS0 is cleared to 0 when both FIFOs become empty.
Rev. 2.00, 03/04, page 332 of 534
Bit
31 to 0
Bit
31 to 0
Bit
31 to 6
5
4
3 to 1
0
Bit Name
D31 to D0 All 0
Bit Name
D31 to D0 All 0
Bit Name

EP3DE
EP2DE

EP0iDE
Initial
Value
Initial
Value
Initial
Value
All 0
0
All 0
0
0
R/W
W
R/W
W
R/W
R
R
R
R
R
Description
Description
Description
Reserved
The write value should always be 0.
Set to 1 when EP3 contains valid data and cleared to 0
when EP3 contains no valid data.
Set to 1 when EP2 contains valid data and cleared to 0
when EP2 contains no valid data.
Reserved
The write value should always be 0.
EP0i Data Enable
Set to 1 when EP0i contains valid data and cleared to 0
when EP0i contains no valid data.
512-byte Transmit FIFO Buffer for EP2
64-byte Transmit FIFO Buffer for EP3
EP3 Data Enable
EP2 Data Enable