C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 166

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C505_9708

Manufacturer Part Number
C505_9708
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
6.5.3 A/D Converter Clock Selection
The ADC uses two clock signals for operation : the conversion clock f
clock f
via the ADC clock prescaler as shown in figure 6-43. The input clock is equal to f
conversion clock f
prescaler must be programmed to a value which assures that the conversion clock does not exceed
1.25 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.
The table in figure 6-43 shows the prescaler ratio which must be selected by ADCL1 and ADCL0
for typical system clock rates. Up to 5 MHz system clock the prescaler ratio 4 is selected. Using a
system clock greater than 5 and less than 10 MHz, the prescaler ratio of at least 8 must be selected.
A prescaler ratio of 16 must be selected when using a system clock greater than 10 MHz.
Figure 6-43
A/D Converter Clock Selection
Semiconductor Group
IN
MCU System Clock
Rate (f
10 MHz
12 MHz
16 MHz
20 MHz
2 MHz
5 MHz
6 MHz
(1/t
IN
). f
OSC
ADC
Condition:
f
ADC
OSC
)
is derived from the C505 system clock f
is limited to a maximum frequency of 1.25 MHz. Therefore, the ADC clock
f
ADC max
ADCL1
Clock Prescaler
f
[MHz]
10
12
16
20
IN
32
16
2
5
6
8
4
< 1.25 MHz
MUX
Prescaler
Ratio
ADCL0
4
4
8
8
16
16
16
f
Conversion Clock
IN
6-104
= f
OSC
Input Clock
=
On-Chip Peripheral Components
f
[MHz]
0.5
1.25
0.75
1.25
0.75
1
1.25
ADC
CLP
1
OSC
f
ADC
f
IN
which is applied at the XTAL pins
ADCL1
0
0
0
0
1
1
1
ADC
Converter
A / D
(=1/t
MCS03299
ADC
C505 / C505C
ADCL0
0
0
1
1
0
0
0
) and the input
1997-08-01
OSC
. The

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