C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 192
C505_9708
Manufacturer Part Number
C505_9708
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C505_9708.pdf
(227 pages)
- Current page: 192 of 227
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Fail Save Mechanisms
C505 / C505C
8.1.3 Starting the Watchdog Timer
The Watchdog Timer can be started by software (bit SWDT in SFR IEN1), but it cannot be stopped
during active mode of the device. If the software fails to clear the watchdog timer an internal reset
will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined
by software (status flag WDTS in IP0 is set). A refresh of the watchdog timer is done by setting bits
WDT (SFR IEN0) and SWDT consecutively. This double instruction sequence has been
implemented to increase system security.
It must be noted, however, that the watchdog timer is halted during the idle mode and power-down
mode of the processor (see section "Power Saving Modes"). It is not possible to use the idle mode
in combination with the watchdog timer function. Therefore, even the watchdog timer cannot reset
the device when one of the power saving modes has been entered accidentally.
Semiconductor Group
8-4
1997-08-01
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