C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 25

• Manufacturer Part Number: C505_9708
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Memory Organization
C505 / C505C
After a reset operation, bit XMAP0 is set. This means that the accesses to XRAM and CAN
controller are generally disabled. In this case, all accesses using MOVX instructions within the
address range of F700 H to FFFF H generate external data memory bus cycles. When XMAP0 is
cleared, the access to XRAM and CAN controller is enabled and all accesses using MOVX
instructions with an address in the range of F700 H to F7FF H will access the CAN controller and
FF00 H to FFFF H will access the internal XRAM. Internal accesses (XMAP0=0) in the address
range gap from F800 H to FEFF H for the C505C (as shown in figure 3-1) will have undefined data.
In the case of the pure C505 microcontroller (without CAN controller), internal accesses in the
address range of F700 H to FEFF H will have undefined data
Bit XMAP0 is hardware protected. If it is cleared once (XRAM and CAN controller access enabled)
it cannot be set by software. Only a reset operation will set the XMAP0 bit again. This hardware
protection mechanism is done by an asymmetric latch at XMAP0 bit. An unintentional disabling of
XRAM and CAN controller could be dangerous since indeterminate values could be read from the
external bus. To avoid this the XMAP0 bit is forced to '1' only by a reset operation. Additionally,
during reset an internal capacitor is charged. So the reset state is a disabled XRAM and CAN
controller. Because of the charge time of the capacitor, XMAP0 bit once written to '0' (that is,
discharging the capacitor) cannot be set to '1' again by software. On the other hand any distortion
(software hang up, noise,...) is not able to charge this capacitor, too. That is, the stable status is
XRAM and CAN controller enabled.
The clear instruction for the XMAP0 bit should be integrated in the program initialization routine
before XRAM or CAN controller is used. In extremely noisy systems the user may have redundant
clear instructions.
Note: The CAN controller peripheral exists in the C505C only.
Semiconductor Group
3-4
1997-08-01