C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 24

• Manufacturer Part Number: C505_9708
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

3.4
The XRAM in the C505 is a memory area that is logically located at the upper end of the external
data memory space, but is integrated on the chip. Because the XRAM is used in the same way as
external data memory the same instruction types (MOVX) must be used for accessing the XRAM.
3.4.1 XRAM/CAN Controller Access Control
Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to XRAM and the CAN
controller. XMAP0 is a general access enable/disable control bit and XMAP1 controls the external
signal generation during XRAM/CAN controller accesses. CAN controller accesses are applicable
only in the case of the C505C versions.
Special Function Register SYSCON (Address B1 H )
Bit
XMAP1
XMAP0
–
When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM and CAN Controller RD and
WR become active and port 0 and 2 drive the actual address/data information which is read/written
from/to XRAM or CAN controller. This feature allows to check the internal data transfers to XRAM
and CAN controller. When port 0 and 2 are used for I/O purposes, the XMAP1 bit should not be set.
Otherwise the I/O function of the port 0 and port 2 lines is interrupted.
Semiconductor Group
B1 H
XRAM Operation
Bit No. MSB
7
–
The functions of the shaded bits are not described here.
Function
XRAM/CAN controller visible access control
Control bit for RD/WR signals during XRAM/CAN Controller accesses. If
addresses are outside the XRAM/CAN controller address range or if
XRAM is disabled, this bit has no effect.
XMAP1 = 0 : The signals RD and WR are not activated during accesses to
XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during
Global XRAM/CAN controller access enable/disable control
XMAP0 = 0 : The access to XRAM and CAN controller is enabled.
XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default
Reserved bits for future use. Read by CPU returns undefined values.
6
–
EALE RMAP CMOD
5
the XRAM/CAN Controller
accesses to XRAM/CAN Controller. In this mode, address
and data information during XRAM/CAN Controller accesses
are visible externally.
after reset!). All MOVX accesses are performed via the
external bus. Further, this bit is hardware protected.
4
3-3
3
2
–
XMAP1
1
Memory Organization
Reset Value : XX100X01 B
XMAP0
LSB
0
C505 / C505C
SYSCON
1997-08-01